blob: 941e7c8933fe27a008961a61f37ecc29473e4bf6 [file] [log] [blame]
wdenk5b845b62002-08-21 21:57:24 +00001/*
wdenk9b7f3842003-10-09 20:09:04 +00002 * (C) Copyright 2003
3 * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
4 *
wdenk5b845b62002-08-21 21:57:24 +00005 * (C) Copyright 2002
6 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenk5b845b62002-08-21 21:57:24 +00009 */
10
11/*
wdenk5b845b62002-08-21 21:57:24 +000012 * Altera FPGA support
13 */
14#include <common.h>
Marek Vasutb9d4df32014-09-16 20:33:54 +020015#include <errno.h>
wdenk9b7f3842003-10-09 20:09:04 +000016#include <ACEX1K.h>
eran liberty4c373a92008-03-27 00:50:49 +010017#include <stratixII.h>
wdenk5b845b62002-08-21 21:57:24 +000018
Marek Vasut9e3a8442014-09-16 20:21:42 +020019/* Define FPGA_DEBUG to 1 to get debug printf's */
20#define FPGA_DEBUG 0
wdenk5b845b62002-08-21 21:57:24 +000021
Marek Vasutff4072c2014-09-16 20:32:51 +020022static int altera_validate(Altera_desc *desc, const char *fn)
23{
24 if (!desc) {
25 printf("%s: NULL descriptor!\n", fn);
Marek Vasutb9d4df32014-09-16 20:33:54 +020026 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020027 }
28
29 if ((desc->family < min_altera_type) ||
30 (desc->family > max_altera_type)) {
31 printf("%s: Invalid family type, %d\n", fn, desc->family);
Marek Vasutb9d4df32014-09-16 20:33:54 +020032 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020033 }
34
35 if ((desc->iface < min_altera_iface_type) ||
36 (desc->iface > max_altera_iface_type)) {
37 printf("%s: Invalid Interface type, %d\n", fn, desc->iface);
Marek Vasutb9d4df32014-09-16 20:33:54 +020038 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020039 }
40
41 if (!desc->size) {
42 printf("%s: NULL part size\n", fn);
Marek Vasutb9d4df32014-09-16 20:33:54 +020043 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020044 }
45
Marek Vasutb9d4df32014-09-16 20:33:54 +020046 return 0;
Marek Vasutff4072c2014-09-16 20:32:51 +020047}
wdenk9b7f3842003-10-09 20:09:04 +000048
wdenk5b845b62002-08-21 21:57:24 +000049/* ------------------------------------------------------------------------- */
Wolfgang Denk74f9b382011-07-30 13:33:49 +000050int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
wdenk5b845b62002-08-21 21:57:24 +000051{
wdenk9b7f3842003-10-09 20:09:04 +000052 int ret_val = FPGA_FAIL; /* assume a failure */
53
Marek Vasutb9d4df32014-09-16 20:33:54 +020054 if (altera_validate(desc, (char *)__func__)) {
Marek Vasut9e3a8442014-09-16 20:21:42 +020055 printf("%s: Invalid device descriptor\n", __func__);
Marek Vasut18221352014-09-16 20:29:24 +020056 return FPGA_FAIL;
57 }
58
59 switch (desc->family) {
60 case Altera_ACEX1K:
61 case Altera_CYC2:
Matthias Fuchsa4400872007-12-27 17:12:34 +010062#if defined(CONFIG_FPGA_ACEX1K)
Marek Vasut18221352014-09-16 20:29:24 +020063 debug_cond(FPGA_DEBUG,
64 "%s: Launching the ACEX1K Loader...\n",
65 __func__);
66 ret_val = ACEX1K_load (desc, buf, bsize);
eran liberty4c373a92008-03-27 00:50:49 +010067#elif defined(CONFIG_FPGA_CYCLON2)
Marek Vasut18221352014-09-16 20:29:24 +020068 debug_cond(FPGA_DEBUG,
69 "%s: Launching the CYCLONE II Loader...\n",
70 __func__);
71 ret_val = CYC2_load (desc, buf, bsize);
wdenk9b7f3842003-10-09 20:09:04 +000072#else
Marek Vasut18221352014-09-16 20:29:24 +020073 printf("%s: No support for ACEX1K devices.\n",
74 __func__);
wdenk9b7f3842003-10-09 20:09:04 +000075#endif
Marek Vasut18221352014-09-16 20:29:24 +020076 break;
wdenk9b7f3842003-10-09 20:09:04 +000077
eran liberty4c373a92008-03-27 00:50:49 +010078#if defined(CONFIG_FPGA_STRATIX_II)
Marek Vasut18221352014-09-16 20:29:24 +020079 case Altera_StratixII:
80 debug_cond(FPGA_DEBUG,
81 "%s: Launching the Stratix II Loader...\n",
82 __func__);
83 ret_val = StratixII_load (desc, buf, bsize);
84 break;
eran liberty4c373a92008-03-27 00:50:49 +010085#endif
Marek Vasut18221352014-09-16 20:29:24 +020086 default:
87 printf("%s: Unsupported family type, %d\n",
88 __func__, desc->family);
wdenk9b7f3842003-10-09 20:09:04 +000089 }
90
91 return ret_val;
wdenk5b845b62002-08-21 21:57:24 +000092}
93
Wolfgang Denk74f9b382011-07-30 13:33:49 +000094int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
wdenk5b845b62002-08-21 21:57:24 +000095{
wdenk9b7f3842003-10-09 20:09:04 +000096 int ret_val = FPGA_FAIL; /* assume a failure */
97
Marek Vasutb9d4df32014-09-16 20:33:54 +020098 if (altera_validate(desc, (char *)__func__)) {
Marek Vasut9e3a8442014-09-16 20:21:42 +020099 printf("%s: Invalid device descriptor\n", __func__);
Marek Vasut18221352014-09-16 20:29:24 +0200100 return FPGA_FAIL;
101 }
102
103 switch (desc->family) {
104 case Altera_ACEX1K:
Matthias Fuchsa4400872007-12-27 17:12:34 +0100105#if defined(CONFIG_FPGA_ACEX)
Marek Vasut18221352014-09-16 20:29:24 +0200106 debug_cond(FPGA_DEBUG,
107 "%s: Launching the ACEX1K Reader...\n",
108 __func__);
109 ret_val = ACEX1K_dump (desc, buf, bsize);
wdenk9b7f3842003-10-09 20:09:04 +0000110#else
Marek Vasut18221352014-09-16 20:29:24 +0200111 printf("%s: No support for ACEX1K devices.\n",
112 __func__);
wdenk9b7f3842003-10-09 20:09:04 +0000113#endif
Marek Vasut18221352014-09-16 20:29:24 +0200114 break;
wdenk9b7f3842003-10-09 20:09:04 +0000115
eran liberty4c373a92008-03-27 00:50:49 +0100116#if defined(CONFIG_FPGA_STRATIX_II)
Marek Vasut18221352014-09-16 20:29:24 +0200117 case Altera_StratixII:
118 debug_cond(FPGA_DEBUG,
119 "%s: Launching the Stratix II Reader...\n",
120 __func__);
121 ret_val = StratixII_dump (desc, buf, bsize);
122 break;
eran liberty4c373a92008-03-27 00:50:49 +0100123#endif
Marek Vasut18221352014-09-16 20:29:24 +0200124 default:
125 printf("%s: Unsupported family type, %d\n",
126 __func__, desc->family);
wdenk9b7f3842003-10-09 20:09:04 +0000127 }
128
129 return ret_val;
wdenk5b845b62002-08-21 21:57:24 +0000130}
131
Marek Vasut18221352014-09-16 20:29:24 +0200132int altera_info(Altera_desc *desc)
wdenk5b845b62002-08-21 21:57:24 +0000133{
wdenk9b7f3842003-10-09 20:09:04 +0000134 int ret_val = FPGA_FAIL;
135
Marek Vasutb9d4df32014-09-16 20:33:54 +0200136 if (altera_validate (desc, (char *)__func__)) {
Marek Vasut18221352014-09-16 20:29:24 +0200137 printf("%s: Invalid device descriptor\n", __func__);
138 return FPGA_FAIL;
139 }
wdenk9b7f3842003-10-09 20:09:04 +0000140
Marek Vasut18221352014-09-16 20:29:24 +0200141 printf("Family: \t");
142 switch (desc->family) {
143 case Altera_ACEX1K:
144 printf("ACEX1K\n");
145 break;
146 case Altera_CYC2:
147 printf("CYCLON II\n");
148 break;
149 case Altera_StratixII:
150 printf("Stratix II\n");
151 break;
152 /* Add new family types here */
153 default:
154 printf("Unknown family type, %d\n", desc->family);
155 }
wdenk9b7f3842003-10-09 20:09:04 +0000156
Marek Vasut18221352014-09-16 20:29:24 +0200157 printf("Interface type:\t");
158 switch (desc->iface) {
159 case passive_serial:
160 printf("Passive Serial (PS)\n");
161 break;
162 case passive_parallel_synchronous:
163 printf("Passive Parallel Synchronous (PPS)\n");
164 break;
165 case passive_parallel_asynchronous:
166 printf("Passive Parallel Asynchronous (PPA)\n");
167 break;
168 case passive_serial_asynchronous:
169 printf("Passive Serial Asynchronous (PSA)\n");
170 break;
171 case altera_jtag_mode: /* Not used */
172 printf("JTAG Mode\n");
173 break;
174 case fast_passive_parallel:
175 printf("Fast Passive Parallel (FPP)\n");
176 break;
177 case fast_passive_parallel_security:
178 printf("Fast Passive Parallel with Security (FPPS)\n");
179 break;
180 /* Add new interface types here */
181 default:
182 printf("Unsupported interface type, %d\n", desc->iface);
183 }
184
185 printf("Device Size: \t%zd bytes\n"
186 "Cookie: \t0x%x (%d)\n",
187 desc->size, desc->cookie, desc->cookie);
wdenk9b7f3842003-10-09 20:09:04 +0000188
Marek Vasut18221352014-09-16 20:29:24 +0200189 if (desc->iface_fns) {
190 printf("Device Function Table @ 0x%p\n", desc->iface_fns);
191 switch (desc->family) {
192 case Altera_ACEX1K:
193 case Altera_CYC2:
Matthias Fuchsa4400872007-12-27 17:12:34 +0100194#if defined(CONFIG_FPGA_ACEX1K)
Marek Vasut18221352014-09-16 20:29:24 +0200195 ACEX1K_info(desc);
Matthias Fuchsa4400872007-12-27 17:12:34 +0100196#elif defined(CONFIG_FPGA_CYCLON2)
Marek Vasut18221352014-09-16 20:29:24 +0200197 CYC2_info(desc);
wdenk9b7f3842003-10-09 20:09:04 +0000198#else
Marek Vasut18221352014-09-16 20:29:24 +0200199 /* just in case */
200 printf("%s: No support for ACEX1K devices.\n",
201 __func__);
wdenk9b7f3842003-10-09 20:09:04 +0000202#endif
Marek Vasut18221352014-09-16 20:29:24 +0200203 break;
eran liberty4c373a92008-03-27 00:50:49 +0100204#if defined(CONFIG_FPGA_STRATIX_II)
Marek Vasut18221352014-09-16 20:29:24 +0200205 case Altera_StratixII:
206 StratixII_info(desc);
207 break;
eran liberty4c373a92008-03-27 00:50:49 +0100208#endif
Marek Vasut18221352014-09-16 20:29:24 +0200209 /* Add new family types here */
210 default:
211 /* we don't need a message here - we give one up above */
212 break;
wdenk9b7f3842003-10-09 20:09:04 +0000213 }
wdenk9b7f3842003-10-09 20:09:04 +0000214 } else {
Marek Vasut18221352014-09-16 20:29:24 +0200215 printf("No Device Function Table.\n");
wdenk9b7f3842003-10-09 20:09:04 +0000216 }
217
Marek Vasut18221352014-09-16 20:29:24 +0200218 ret_val = FPGA_SUCCESS;
219
wdenk9b7f3842003-10-09 20:09:04 +0000220 return ret_val;
221}