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git01.mediatek.com / filogic / uboot / cbb6566aca267bc693b7ab000a7b771740f19a51 / . / arch / powerpc / include / asm / fsl_serdes.h
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Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]1/*
2 * Copyright 2010 Freescale Semiconductor, Inc.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]5 */
6
Anton Vorontsov202f9e02008-03-24 17:40:32 +0300[diff] [blame]7#ifndef __FSL_SERDES_H
8#define __FSL_SERDES_H
9
10#include <config.h>
11
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]12enum srds_prtcl {
13 NONE = 0,
14 PCIE1,
15 PCIE2,
16 PCIE3,
17 PCIE4,
18 SATA1,
19 SATA2,
20 SRIO1,
21 SRIO2,
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]22 SGMII_FM1_DTSEC1,
23 SGMII_FM1_DTSEC2,
24 SGMII_FM1_DTSEC3,
25 SGMII_FM1_DTSEC4,
26 SGMII_FM1_DTSEC5,
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]27 SGMII_FM1_DTSEC6,
28 SGMII_FM1_DTSEC9,
29 SGMII_FM1_DTSEC10,
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]30 SGMII_FM2_DTSEC1,
31 SGMII_FM2_DTSEC2,
32 SGMII_FM2_DTSEC3,
33 SGMII_FM2_DTSEC4,
Timur Tabi7920fb12012-08-14 06:47:21 +0000[diff] [blame]34 SGMII_FM2_DTSEC5,
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]35 SGMII_FM2_DTSEC6,
36 SGMII_FM2_DTSEC9,
37 SGMII_FM2_DTSEC10,
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]38 SGMII_TSEC1,
39 SGMII_TSEC2,
40 SGMII_TSEC3,
41 SGMII_TSEC4,
42 XAUI_FM1,
43 XAUI_FM2,
44 AURORA,
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]45 CPRI1,
46 CPRI2,
47 CPRI3,
48 CPRI4,
49 CPRI5,
50 CPRI6,
51 CPRI7,
52 CPRI8,
53 XAUI_FM1_MAC9,
54 XAUI_FM1_MAC10,
55 XAUI_FM2_MAC9,
56 XAUI_FM2_MAC10,
57 HIGIG_FM1_MAC9,
58 HIGIG_FM1_MAC10,
59 HIGIG_FM2_MAC9,
60 HIGIG_FM2_MAC10,
61 QSGMII_FM1_A, /* A indicates MACs 1-4 */
62 QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
63 QSGMII_FM2_A,
64 QSGMII_FM2_B,
65 XFI_FM1_MAC9,
66 XFI_FM1_MAC10,
67 XFI_FM2_MAC9,
68 XFI_FM2_MAC10,
69 INTERLAKEN,
York Sun46571362013-03-25 07:40:06 +0000[diff] [blame]70 SGMII_SW1_DTSEC1, /* SW indicates on L2 switch */
71 SGMII_SW1_DTSEC2,
72 SGMII_SW1_DTSEC3,
73 SGMII_SW1_DTSEC4,
74 SGMII_SW1_DTSEC5,
75 SGMII_SW1_DTSEC6,
76 QSGMII_SW1_A, /* SW indicates on L2 swtich */
77 QSGMII_SW1_B,
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]78};
Anton Vorontsov202f9e02008-03-24 17:40:32 +0300[diff] [blame]79
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]80enum srds {
81 FSL_SRDS_1 = 0,
82 FSL_SRDS_2 = 1,
83 FSL_SRDS_3 = 2,
84 FSL_SRDS_4 = 3,
85};
86
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]87int is_serdes_configured(enum srds_prtcl device);
Kumar Gala86853d42010-05-22 13:21:39 -0500[diff] [blame]88void fsl_serdes_init(void);
Anton Vorontsov202f9e02008-03-24 17:40:32 +0300[diff] [blame]89
Emil Medvef6651e62010-08-31 22:57:36 -0500[diff] [blame]90#ifdef CONFIG_FSL_CORENET
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]91#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
92int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
Shaveta Leekhac404d612013-07-02 14:42:07 +0530[diff] [blame]93enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]94#else
Emil Medvef6651e62010-08-31 22:57:36 -0500[diff] [blame]95int serdes_get_first_lane(enum srds_prtcl device);
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]96#endif
Emil Medveb01c81f2010-08-31 22:57:38 -0500[diff] [blame]97#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
98void serdes_reset_rx(enum srds_prtcl device);
99#endif
Emil Medvef6651e62010-08-31 22:57:36 -0500[diff] [blame]100#endif
101
Anton Vorontsov202f9e02008-03-24 17:40:32 +0300[diff] [blame]102#endif /* __FSL_SERDES_H */