Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the Motorola MC5275EVB board. |
| 4 | * |
| 5 | * By Arthur Shipkowski <art@videon-central.com> |
| 6 | * Copyright (C) 2005 Videon Central, Inc. |
| 7 | * |
| 8 | * Based off of M5272C3 board code by Josef Baumgartner |
| 9 | * <josef.baumgartner@telex.de> |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | /* |
| 13 | * board/config.h - configuration options, board specific |
| 14 | */ |
| 15 | |
| 16 | #ifndef _M5275EVB_H |
| 17 | #define _M5275EVB_H |
| 18 | |
| 19 | /* |
| 20 | * High Level Configuration Options |
| 21 | * (easy to change) |
| 22 | */ |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 23 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 24 | #define CFG_SYS_UART_PORT (0) |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 25 | |
| 26 | /* Configuration for environment |
| 27 | * Environment is embedded in u-boot in the second sector of the flash |
| 28 | */ |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 29 | |
angelo@sysam.it | 6312a95 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 30 | #define LDS_BOARD_TEXT \ |
Simon Glass | 547cb40 | 2017-08-03 12:21:49 -0600 | [diff] [blame] | 31 | . = DEFINED(env_offset) ? env_offset : .; \ |
| 32 | env/embedded.o(.text); |
angelo@sysam.it | 6312a95 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 33 | |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 34 | /* Available command configuration */ |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 35 | |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 36 | /* I2C */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 37 | #define CFG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) |
| 38 | #define CFG_SYS_I2C_PINMUX_CLR (0xFFF0) |
| 39 | #define CFG_SYS_I2C_PINMUX_SET (0x000F) |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 40 | |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 41 | #define CFG_EXTRA_ENV_SETTINGS \ |
TsiChung Liew | 23cc28c | 2010-03-10 16:33:03 -0600 | [diff] [blame] | 42 | "netdev=eth0\0" \ |
| 43 | "loadaddr=10000\0" \ |
| 44 | "uboot=u-boot.bin\0" \ |
| 45 | "load=tftp ${loadaddr} ${uboot}\0" \ |
| 46 | "upd=run load; run prog\0" \ |
| 47 | "prog=prot off ffe00000 ffe3ffff;" \ |
| 48 | "era ffe00000 ffe3ffff;" \ |
| 49 | "cp.b ${loadaddr} ffe00000 ${filesize};"\ |
| 50 | "save\0" \ |
| 51 | "" |
| 52 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 53 | #define CFG_SYS_CLK 150000000 |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 54 | |
| 55 | /* |
| 56 | * Low Level Configuration Settings |
| 57 | * (address mappings, register initial values, etc.) |
| 58 | * You should know what you are doing if you make changes here. |
| 59 | */ |
| 60 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 61 | #define CFG_SYS_MBAR 0x40000000 |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 62 | |
| 63 | /*----------------------------------------------------------------------- |
| 64 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 65 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 66 | #define CFG_SYS_INIT_RAM_ADDR 0x20000000 |
| 67 | #define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 68 | |
| 69 | /*----------------------------------------------------------------------- |
| 70 | * Start addresses for the final memory configuration |
| 71 | * (Set up by the startup code) |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 72 | * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 73 | */ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 74 | #define CFG_SYS_SDRAM_BASE 0x00000000 |
| 75 | #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 76 | #define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 77 | |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 78 | /* |
| 79 | * For booting Linux, the board info and command line data |
| 80 | * have to be in the first 8 MB of memory, since this is |
| 81 | * the maximum mapped by the Linux kernel during initialization ?? |
| 82 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 83 | #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 84 | |
| 85 | /*----------------------------------------------------------------------- |
| 86 | * FLASH organization |
| 87 | */ |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 88 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 89 | #define CFG_SYS_FLASH_SIZE 0x200000 |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 90 | |
| 91 | /*----------------------------------------------------------------------- |
| 92 | * Cache Configuration |
| 93 | */ |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 94 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 95 | #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ |
| 96 | CFG_SYS_INIT_RAM_SIZE - 8) |
| 97 | #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ |
| 98 | CFG_SYS_INIT_RAM_SIZE - 4) |
| 99 | #define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) |
| 100 | #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 101 | CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 102 | CF_ACR_EN | CF_ACR_SM_ALL) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 103 | #define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 104 | CF_CACR_DISD | CF_CACR_INVI | \ |
| 105 | CF_CACR_CEIB | CF_CACR_DCM | \ |
| 106 | CF_CACR_EUSP) |
| 107 | |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 108 | /*----------------------------------------------------------------------- |
| 109 | * Memory bank definitions |
| 110 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 111 | #define CFG_SYS_CS0_BASE 0xffe00000 |
| 112 | #define CFG_SYS_CS0_CTRL 0x00001980 |
| 113 | #define CFG_SYS_CS0_MASK 0x001F0001 |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 114 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 115 | #define CFG_SYS_CS1_BASE 0x30000000 |
| 116 | #define CFG_SYS_CS1_CTRL 0x00001900 |
| 117 | #define CFG_SYS_CS1_MASK 0x00070001 |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 118 | |
Angelo Dureghello | 49becce | 2023-02-25 23:25:26 +0100 | [diff] [blame] | 119 | |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 120 | #endif /* _M5275EVB_H */ |