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git01.mediatek.com / filogic / uboot / 68d77afe0de9917942b2880ff5966a7c74285540 / . / arch / arm / dts / imx8mm-verdin-wifi-dev-u-boot.dtsi
blob: 8b397f535c148810ce672cb56c27486796322559 [file] [log] [blame]
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2020-2022 Toradex
4 */
5
6#include "imx8mm-u-boot.dtsi"
7
8/ {
Emanuele Ghidoliff939c22024-02-23 10:11:40 +0100[diff] [blame]9 aliases {
10 eeprom0 = &eeprom_module;
11 eeprom1 = &eeprom_carrier_board;
12 eeprom2 = &eeprom_display_adapter;
13 };
14
Emanuele Ghidoli26b5cba2024-02-23 10:11:41 +0100[diff] [blame]15 sysinfo {
16 compatible = "toradex,sysinfo";
17 };
18
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]19 wdt-reboot {
20 compatible = "wdt-reboot";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]22 wdt = <&wdog1>;
23 };
24};
25
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]26&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]27 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]28};
29
30&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]31 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]32};
33
Marcel Ziswiler8d322832023-08-23 00:17:25 +0200[diff] [blame]34&aips4 {
35 bootph-pre-ram;
36};
37
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]38&binman_uboot {
39 offset = <0x5fc00>;
40};
41
42&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]44};
45
46&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]47 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]48};
49
50&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]52};
53
54&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]55 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]56};
57
58&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-pre-ram;
Andrejs Cainikovs5ab25a12023-07-11 11:09:16 +0200[diff] [blame]60
61 ctrl-sleep-moci-hog {
62 bootph-pre-ram;
Stefan Eichenberger11e22d32024-04-17 10:49:02 +0200[diff] [blame]63 gpio-hog;
64 output-high;
65 gpios = <1 GPIO_ACTIVE_HIGH>;
66 line-name = "CTRL_SLEEP_MOCI#";
67
Andrejs Cainikovs5ab25a12023-07-11 11:09:16 +0200[diff] [blame]68 };
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]69};
70
71&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]73
74 eeprom_module: eeprom@50 {
75 compatible = "i2c-eeprom";
76 pagesize = <16>;
77 reg = <0x50>;
78 };
79};
80
81&i2c2 {
82 status = "okay";
83};
84
85&i2c4 {
86 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
87 eeprom_display_adapter: eeprom@50 {
88 compatible = "i2c-eeprom";
89 pagesize = <16>;
90 reg = <0x50>;
91 };
92
93 /* EEPROM on carrier board */
94 eeprom_carrier_board: eeprom@57 {
95 compatible = "i2c-eeprom";
96 pagesize = <16>;
97 reg = <0x57>;
98 };
99};
100
Andrejs Cainikovs5ab25a12023-07-11 11:09:16 +0200[diff] [blame]101&pinctrl_ctrl_sleep_moci {
102 bootph-pre-ram;
103};
104
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]105&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]106 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]107};
108
109&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]110 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]111};
112
113&pinctrl_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]114 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]115};
116
117&pinctrl_usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]118 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]119};
120
121&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]122 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]123};
124
125&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]126 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]127};
128
129&uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]130 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]131};
132
Marcel Ziswiler8d322832023-08-23 00:17:25 +0200[diff] [blame]133&usbmisc1 {
134 bootph-pre-ram;
135};
136
137/* Verdin USB_1 */
138&usbotg1 {
139 bootph-pre-ram;
140};
141
142&usbphynop1 {
143 bootph-pre-ram;
144};
145
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]146&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]147 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]148};
149
150&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]151 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]152};
153
154&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]155 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]156};
157
158&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]159 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]160};