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git01.mediatek.com / filogic / uboot / f43bf5dd4c482772e088b251fd2fdaabfa7d0595 / . / drivers / power / pmic / as3722.c
blob: 63df6133549acb3b7ae660aaba2e73be0a9abc49 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]2/*
3 * Copyright (C) 2014 NVIDIA Corporation
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]4 */
5
6#define pr_fmt(fmt) "as3722: " fmt
7
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
11#include <fdtdec.h>
12#include <i2c.h>
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]13#include <dm/lists.h>
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]14#include <power/as3722.h>
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]15#include <power/pmic.h>
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]16
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]17#define AS3722_NUM_OF_REGS 0x92
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]18
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]19static int as3722_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]20{
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]21 int ret;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]22
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]23 ret = dm_i2c_read(dev, reg, buff, len);
24 if (ret < 0)
25 return ret;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]26
27 return 0;
28}
29
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]30static int as3722_write(struct udevice *dev, uint reg, const uint8_t *buff,
31 int len)
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]32{
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]33 int ret;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]34
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]35 ret = dm_i2c_write(dev, reg, buff, len);
36 if (ret < 0)
37 return ret;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]38
39 return 0;
40}
41
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]42static int as3722_read_id(struct udevice *dev, uint *idp, uint *revisionp)
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]43{
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]44 int ret;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]45
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]46 ret = pmic_reg_read(dev, AS3722_ASIC_ID1);
47 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900[diff] [blame]48 pr_err("failed to read ID1 register: %d", ret);
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]49 return ret;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]50 }
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]51 *idp = ret;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]52
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]53 ret = pmic_reg_read(dev, AS3722_ASIC_ID2);
54 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900[diff] [blame]55 pr_err("failed to read ID2 register: %d", ret);
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]56 return ret;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]57 }
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]58 *revisionp = ret;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]59
60 return 0;
61}
62
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]63/* TODO(treding@nvidia.com): Add proper regulator support to avoid this */
64int as3722_sd_set_voltage(struct udevice *dev, unsigned int sd, u8 value)
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]65{
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]66 int ret;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]67
68 if (sd > 6)
69 return -EINVAL;
70
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]71 ret = pmic_reg_write(dev, AS3722_SD_VOLTAGE(sd), value);
72 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900[diff] [blame]73 pr_err("failed to write SD%u voltage register: %d", sd, ret);
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]74 return ret;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]75 }
76
77 return 0;
78}
79
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]80int as3722_ldo_set_voltage(struct udevice *dev, unsigned int ldo, u8 value)
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]81{
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]82 int ret;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]83
84 if (ldo > 11)
85 return -EINVAL;
86
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]87 ret = pmic_reg_write(dev, AS3722_LDO_VOLTAGE(ldo), value);
88 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900[diff] [blame]89 pr_err("failed to write LDO%u voltage register: %d", ldo,
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]90 ret);
91 return ret;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]92 }
93
94 return 0;
95}
96
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]97static int as3722_probe(struct udevice *dev)
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]98{
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]99 uint id, revision;
100 int ret;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]101
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]102 ret = as3722_read_id(dev, &id, &revision);
103 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900[diff] [blame]104 pr_err("failed to read ID: %d", ret);
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]105 return ret;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]106 }
107
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]108 if (id != AS3722_DEVICE_ID) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900[diff] [blame]109 pr_err("unknown device");
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]110 return -ENOENT;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]111 }
112
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]113 debug("AS3722 revision %#x found on I2C bus %s\n", revision, dev->name);
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]114
115 return 0;
116}
117
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]118#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
119static const struct pmic_child_info pmic_children_info[] = {
120 { .prefix = "sd", .driver = "as3722_stepdown"},
121 { .prefix = "ldo", .driver = "as3722_ldo"},
122 { },
123};
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]124
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]125static int as3722_bind(struct udevice *dev)
126{
127 struct udevice *gpio_dev;
128 ofnode regulators_node;
129 int children;
130 int ret;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]131
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]132 regulators_node = dev_read_subnode(dev, "regulators");
133 if (!ofnode_valid(regulators_node)) {
134 debug("%s: %s regulators subnode not found\n", __func__,
135 dev->name);
136 return -ENXIO;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]137 }
138
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]139 children = pmic_bind_children(dev, regulators_node, pmic_children_info);
140 if (!children)
141 debug("%s: %s - no child found\n", __func__, dev->name);
142 ret = device_bind_driver(dev, "gpio_as3722", "gpio_as3722", &gpio_dev);
143 if (ret) {
144 debug("%s: Cannot bind GPIOs (ret=%d)\n", __func__, ret);
145 return ret;
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]146 }
147
148 return 0;
149}
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]150#endif
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]151
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]152static int as3722_reg_count(struct udevice *dev)
Simon Glass053da132015-04-14 21:03:26 -0600[diff] [blame]153{
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]154 return AS3722_NUM_OF_REGS;
Simon Glass053da132015-04-14 21:03:26 -0600[diff] [blame]155}
156
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]157static struct dm_pmic_ops as3722_ops = {
158 .reg_count = as3722_reg_count,
159 .read = as3722_read,
160 .write = as3722_write,
161};
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]162
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]163static const struct udevice_id as3722_ids[] = {
164 { .compatible = "ams,as3722" },
165 { }
166};
Thierry Reding09c0cf22014-12-09 22:25:05 -0700[diff] [blame]167
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]168U_BOOT_DRIVER(pmic_as3722) = {
169 .name = "as3722_pmic",
170 .id = UCLASS_PMIC,
171 .of_match = as3722_ids,
172#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
173 .bind = as3722_bind,
174#endif
175 .probe = as3722_probe,
176 .ops = &as3722_ops,
177};