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git01.mediatek.com / filogic / uboot / f3dbe50196d904d002f3341b5108b998530ae1a4 / . / drivers / mtd / spi / sf_params.c
blob: 30875b36602accf302a8920ad9f3f2450db46b2b [file] [log] [blame]
Jagannadha Sutradharudu Teki20e45bc2013-12-23 23:34:42 +0530[diff] [blame]1/*
2 * SPI flash Params table
3 *
4 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
Simon Glassdef92152014-10-13 23:41:55 -0600[diff] [blame]10#include <spi.h>
Jagannadha Sutradharudu Teki20e45bc2013-12-23 23:34:42 +0530[diff] [blame]11#include <spi_flash.h>
12
13#include "sf_internal.h"
14
15/* SPI/QSPI flash device params structure */
16const struct spi_flash_params spi_flash_params_table[] = {
17#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
Jagannadha Sutradharudu Teki29e63912014-12-12 19:36:11 +0530[diff] [blame]18 {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K},
19 {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
20 {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
21 {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K},
22 {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K},
23 {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
24 {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
25 {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
Jagannadha Sutradharudu Teki20e45bc2013-12-23 23:34:42 +0530[diff] [blame]26#endif
27#ifdef CONFIG_SPI_FLASH_EON /* EON */
Jagannadha Sutradharudu Teki29e63912014-12-12 19:36:11 +0530[diff] [blame]28 {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, RD_NORM, 0},
29 {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
30 {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, RD_NORM, 0},
31 {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, RD_NORM, 0},
Jagannadha Sutradharudu Teki20e45bc2013-12-23 23:34:42 +0530[diff] [blame]32#endif
33#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
Jagannadha Sutradharudu Teki29e63912014-12-12 19:36:11 +0530[diff] [blame]34 {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
35 {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
Jagannadha Sutradharudu Teki20e45bc2013-12-23 23:34:42 +0530[diff] [blame]36#endif
37#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
Jagannadha Sutradharudu Teki29e63912014-12-12 19:36:11 +0530[diff] [blame]38 {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, RD_NORM, 0},
39 {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, RD_NORM, 0},
40 {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, RD_NORM, 0},
41 {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, RD_NORM, 0},
42 {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, RD_NORM, 0},
43 {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, RD_NORM, 0},
Jagannadha Sutradharudu Teki1d10e582013-12-26 14:16:50 +0530[diff] [blame]44 {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
45 {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP},
46 {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP},
47 {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
Jagannadha Sutradharudu Teki20e45bc2013-12-23 23:34:42 +0530[diff] [blame]48#endif
49#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
Jagannadha Sutradharudu Teki29e63912014-12-12 19:36:11 +0530[diff] [blame]50 {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, RD_NORM, 0},
51 {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, RD_NORM, 0},
52 {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, RD_NORM, 0},
53 {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, RD_NORM, 0},
Jagannadha Sutradharudu Teki20e45bc2013-12-23 23:34:42 +0530[diff] [blame]54 {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP},
55 {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP},
56 {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP},
57 {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP},
Marek Vasutf6e25272014-01-15 15:32:09 +0100[diff] [blame]58 {"S25FL128S_256K", 0x012018, 0x4d00, 256 * 1024, 64, RD_FULL, WR_QPP},
Jagannadha Sutradharudu Teki20e45bc2013-12-23 23:34:42 +0530[diff] [blame]59 {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP},
Marek Vasut34985622014-01-15 15:29:43 +0100[diff] [blame]60 {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP},
Jagannadha Sutradharudu Teki20e45bc2013-12-23 23:34:42 +0530[diff] [blame]61 {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
Marek Vasut34985622014-01-15 15:29:43 +0100[diff] [blame]62 {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP},
Jagannadha Sutradharudu Teki20e45bc2013-12-23 23:34:42 +0530[diff] [blame]63 {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP},
Siva Durga Prasad Paladugub219e822014-04-25 15:47:13 +0200[diff] [blame]64 {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP},
Jagannadha Sutradharudu Teki20e45bc2013-12-23 23:34:42 +0530[diff] [blame]65#endif
66#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
Jagannadha Sutradharudu Teki29e63912014-12-12 19:36:11 +0530[diff] [blame]67 {"M25P10", 0x202011, 0x0, 32 * 1024, 4, RD_NORM, 0},
68 {"M25P20", 0x202012, 0x0, 64 * 1024, 4, RD_NORM, 0},
69 {"M25P40", 0x202013, 0x0, 64 * 1024, 8, RD_NORM, 0},
70 {"M25P80", 0x202014, 0x0, 64 * 1024, 16, RD_NORM, 0},
71 {"M25P16", 0x202015, 0x0, 64 * 1024, 32, RD_NORM, 0},
72 {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, RD_NORM, 0},
Nikita Kiryanov257ede92014-08-20 15:08:51 +0300[diff] [blame]73 {"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_EXTN, 0},
Jagannadha Sutradharudu Teki29e63912014-12-12 19:36:11 +0530[diff] [blame]74 {"M25P32", 0x202016, 0x0, 64 * 1024, 64, RD_NORM, 0},
75 {"M25P64", 0x202017, 0x0, 64 * 1024, 128, RD_NORM, 0},
76 {"M25P128", 0x202018, 0x0, 256 * 1024, 64, RD_NORM, 0},
77 {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
Jagannadha Sutradharudu Teki20e45bc2013-12-23 23:34:42 +0530[diff] [blame]78 {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
79 {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
80 {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
81 {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
Siva Durga Prasad Paladugubdc797c2014-01-08 11:27:07 +0530[diff] [blame]82 {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
83 {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
Jagannadha Sutradharudu Teki20e45bc2013-12-23 23:34:42 +0530[diff] [blame]84 {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
85 {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
86 {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
87 {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},
88 {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
89 {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
90#endif
91#ifdef CONFIG_SPI_FLASH_SST /* SST */
Jagannadha Sutradharudu Teki7f0fd702014-12-12 19:36:14 +0530[diff] [blame]92 {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR},
93 {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR},
94 {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K | SST_WR},
95 {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K | SST_WR},
Jagannadha Sutradharudu Teki29e63912014-12-12 19:36:11 +0530[diff] [blame]96 {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
Jagannadha Sutradharudu Teki7f0fd702014-12-12 19:36:14 +0530[diff] [blame]97 {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM, SECT_4K | SST_WR},
98 {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM, SECT_4K | SST_WR},
99 {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K | SST_WR},
100 {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR},
101 {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR},
Jagannadha Sutradharudu Teki20e45bc2013-12-23 23:34:42 +0530[diff] [blame]102#endif
103#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
Jagannadha Sutradharudu Teki29e63912014-12-12 19:36:11 +0530[diff] [blame]104 {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, RD_NORM, 0},
105 {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, RD_NORM, 0},
106 {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, RD_NORM, 0},
107 {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
108 {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K},
109 {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
110 {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
Jagannadha Sutradharudu Teki20e45bc2013-12-23 23:34:42 +0530[diff] [blame]111 {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
112 {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
113 {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
114 {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
115 {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
116 {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K},
117 {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
118 {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
119 {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
120 {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
121 {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K},
122#endif
Simon Glass49c753d2014-09-15 06:33:36 -0600[diff] [blame]123 {}, /* Empty entry to terminate the list */
Jagannadha Sutradharudu Teki20e45bc2013-12-23 23:34:42 +0530[diff] [blame]124 /*
125 * Note:
126 * Below paired flash devices has similar spi_flash params.
127 * (S25FL129P_64K, S25FL128S_64K)
128 * (W25Q80BL, W25Q80BV)
129 * (W25Q16CL, W25Q16DV)
130 * (W25Q32BV, W25Q32FV_SPI)
131 * (W25Q64CV, W25Q64FV_SPI)
132 * (W25Q128BV, W25Q128FV_SPI)
133 * (W25Q32DW, W25Q32FV_QPI)
134 * (W25Q64DW, W25Q64FV_QPI)
135 * (W25Q128FW, W25Q128FV_QPI)
136 */
137};