blob: 11ce023ec64aa5e59fe315b8b6a27ca5eb578253 [file] [log] [blame]
Dinesh Maniyamf3d03822025-02-27 00:18:15 +08001# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mtd/cadence,nand.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence NAND controller
8
9maintainers:
10 - Dinesh Maniyam <dinesh.maniyam@intel.com>
11
12properties:
13 compatible:
14 enum:
15 - cdns,nand
16
17 reg-names:
18 description: |
19 There are two register regions:
20 reg: register interface
21 sdma: host data/command interface
22 items:
23 - const: reg
24 - const: sdma
25
26 reg:
27 minItems: 2
28 maxItems: 2
29
30 interrupts:
31 maxItems: 1
32
33 clocks:
34 description: |
35 There is one controller core clock
36 maxItems: 1
37
38 resets:
39 description: |
40 There are two resets:
41 controller core reset
42 combo-phy register reset
43 minItems: 1
44 maxItems: 2
45
46 cdns,board-delay-ps:
47 description: |
48 Estimated Board delay. The value includes the total
49 round trip delay for the signals and is used for deciding on values
50 associated with data read capture. The example formula for SDR mode is
51 the following:
52 board delay = RE#PAD delay + PCB trace to device + PCB trace from device
53 + DQ PAD delay
54 enum:
55 - 4830
56
57patternProperties:
58 "^nand@[a-f0-9]$":
59 type: object
60 properties:
61 compatible:
62 const: cdns,nand
63
64 reg:
65 maxItems: 1
66
67 label:
68 maxItems: 1
69
70required:
71 - compatible
72 - reg
73 - interrupts
74 - clocks
75 - cdns,board-delay-ps
76
77unevaluatedProperties: false
78
79examples:
80 - |
81 nand-controller@60000000 {
82 compatible = "cdns,nand";
83 reg = <0x60000000 0x10000>, <0x80000000 0x1000>;
84 reg-names = "reg", "sdma";
85 #address-cells = <1>;
86 #size-cells = <0>;
87 clocks = <&clk>;
88 cdns,board-delay-ps = <4830>;
89 interrupts = <2 0>;
90 nand@0 {
91 label = "nand-0";
92 reg = <0>;
93 };
94 nand@1 {
95 label = "nand-1";
96 reg = <1>;
97 };
98 };