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git01.mediatek.com / filogic / uboot / f3c6e440b31632cb153b22611988a0f30dd4c52b / . / arch / xtensa / include / asm / arch-de212 / tie-asm.h
blob: 7213550b8a848be4d831ee5516a1cfa66fb2ced9 [file] [log] [blame]
Max Filippov49739402016-08-10 18:36:47 +0300[diff] [blame]1/*
2 * This header file contains assembly-language definitions (assembly
3 * macros, etc.) for this specific Xtensa processor's TIE extensions
4 * and options. It is customized to this Xtensa processor configuration.
5 * This file is autogenerated, please do not edit.
6 *
7 * Copyright (C) 1999-2015 Cadence Design Systems Inc.
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12#ifndef _XTENSA_CORE_TIE_ASM_H
13#define _XTENSA_CORE_TIE_ASM_H
14
15/* Selection parameter values for save-area save/restore macros: */
16/* Option vs. TIE: */
17#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
18#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
19#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
20/* Whether used automatically by compiler: */
21#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
22#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
23#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
24/* ABI handling across function calls: */
25#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
26#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
27#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
28#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
29/* Misc */
30#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
31#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
32 | ((ccuse) & XTHAL_SAS_ANYCC) \
33 | ((abi) & XTHAL_SAS_ANYABI) )
34
35
36 /*
37 * Macro to store all non-coprocessor (extra) custom TIE and optional state
38 * (not including zero-overhead loop registers).
39 * Required parameters:
40 * ptr Save area pointer address register (clobbered)
41 * (register must contain a 4 byte aligned address).
42 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
43 * registers are clobbered, the remaining are unused).
44 * Optional parameters:
45 * continue If macro invoked as part of a larger store sequence, set to 1
46 * if this is not the first in the sequence. Defaults to 0.
47 * ofs Offset from start of larger sequence (from value of first ptr
48 * in sequence) at which to store. Defaults to next available space
49 * (or 0 if <continue> is 0).
50 * select Select what category(ies) of registers to store, as a bitmask
51 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
52 * alloc Select what category(ies) of registers to allocate; if any
53 * category is selected here that is not in <select>, space for
54 * the corresponding registers is skipped without doing any store.
55 */
56 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
57 xchal_sa_start \continue, \ofs
58 // Optional caller-saved registers used by default by the compiler:
59 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
60 xchal_sa_align \ptr, 0, 1016, 4, 4
61 rsr.ACCLO \at1 // MAC16 option
62 s32i \at1, \ptr, .Lxchal_ofs_+0
63 rsr.ACCHI \at1 // MAC16 option
64 s32i \at1, \ptr, .Lxchal_ofs_+4
65 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
66 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
67 xchal_sa_align \ptr, 0, 1016, 4, 4
68 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
69 .endif
70 // Optional caller-saved registers not used by default by the compiler:
71 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
72 xchal_sa_align \ptr, 0, 1004, 4, 4
73 rsr.SCOMPARE1 \at1 // conditional store option
74 s32i \at1, \ptr, .Lxchal_ofs_+0
75 rsr.M0 \at1 // MAC16 option
76 s32i \at1, \ptr, .Lxchal_ofs_+4
77 rsr.M1 \at1 // MAC16 option
78 s32i \at1, \ptr, .Lxchal_ofs_+8
79 rsr.M2 \at1 // MAC16 option
80 s32i \at1, \ptr, .Lxchal_ofs_+12
81 rsr.M3 \at1 // MAC16 option
82 s32i \at1, \ptr, .Lxchal_ofs_+16
83 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
84 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
85 xchal_sa_align \ptr, 0, 1004, 4, 4
86 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
87 .endif
88 .endm // xchal_ncp_store
89
90 /*
91 * Macro to load all non-coprocessor (extra) custom TIE and optional state
92 * (not including zero-overhead loop registers).
93 * Required parameters:
94 * ptr Save area pointer address register (clobbered)
95 * (register must contain a 4 byte aligned address).
96 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
97 * registers are clobbered, the remaining are unused).
98 * Optional parameters:
99 * continue If macro invoked as part of a larger load sequence, set to 1
100 * if this is not the first in the sequence. Defaults to 0.
101 * ofs Offset from start of larger sequence (from value of first ptr
102 * in sequence) at which to load. Defaults to next available space
103 * (or 0 if <continue> is 0).
104 * select Select what category(ies) of registers to load, as a bitmask
105 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
106 * alloc Select what category(ies) of registers to allocate; if any
107 * category is selected here that is not in <select>, space for
108 * the corresponding registers is skipped without doing any load.
109 */
110 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
111 xchal_sa_start \continue, \ofs
112 // Optional caller-saved registers used by default by the compiler:
113 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
114 xchal_sa_align \ptr, 0, 1016, 4, 4
115 l32i \at1, \ptr, .Lxchal_ofs_+0
116 wsr.ACCLO \at1 // MAC16 option
117 l32i \at1, \ptr, .Lxchal_ofs_+4
118 wsr.ACCHI \at1 // MAC16 option
119 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
120 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
121 xchal_sa_align \ptr, 0, 1016, 4, 4
122 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
123 .endif
124 // Optional caller-saved registers not used by default by the compiler:
125 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
126 xchal_sa_align \ptr, 0, 1004, 4, 4
127 l32i \at1, \ptr, .Lxchal_ofs_+0
128 wsr.SCOMPARE1 \at1 // conditional store option
129 l32i \at1, \ptr, .Lxchal_ofs_+4
130 wsr.M0 \at1 // MAC16 option
131 l32i \at1, \ptr, .Lxchal_ofs_+8
132 wsr.M1 \at1 // MAC16 option
133 l32i \at1, \ptr, .Lxchal_ofs_+12
134 wsr.M2 \at1 // MAC16 option
135 l32i \at1, \ptr, .Lxchal_ofs_+16
136 wsr.M3 \at1 // MAC16 option
137 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
138 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
139 xchal_sa_align \ptr, 0, 1004, 4, 4
140 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20
141 .endif
142 .endm // xchal_ncp_load
143
144
145#define XCHAL_NCP_NUM_ATMPS 1
146
147#define XCHAL_SA_NUM_ATMPS 1
148
149#endif /*_XTENSA_CORE_TIE_ASM_H*/
150