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git01.mediatek.com / filogic / uboot / f3816f4e933a1833612feff18b9d725fcf03e128 / . / arch / arm / include / asm / arch-davinci / pll_defs.h
blob: d083cccadb3dd8fc9f76452dbf783683fdeb1403 [file] [log] [blame]
Heiko Schocherf1084d62011-11-01 20:00:31 +0000[diff] [blame]1/*
2 * Copyright (C) 2011
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocherf1084d62011-11-01 20:00:31 +0000[diff] [blame]6 */
7#ifndef _DV_PLL_DEFS_H_
8#define _DV_PLL_DEFS_H_
9
10struct dv_pll_regs {
11 unsigned int pid; /* 0x00 */
12 unsigned char rsvd0[224]; /* 0x04 */
13 unsigned int rstype; /* 0xe4 */
14 unsigned char rsvd1[24]; /* 0xe8 */
15 unsigned int pllctl; /* 0x100 */
16 unsigned char rsvd2[4]; /* 0x104 */
17 unsigned int secctl; /* 0x108 */
18 unsigned int rv; /* 0x10c */
19 unsigned int pllm; /* 0x110 */
20 unsigned int prediv; /* 0x114 */
21 unsigned int plldiv1; /* 0x118 */
22 unsigned int plldiv2; /* 0x11c */
23 unsigned int plldiv3; /* 0x120 */
24 unsigned int oscdiv1; /* 0x124 */
25 unsigned int postdiv; /* 0x128 */
26 unsigned int bpdiv; /* 0x12c */
27 unsigned char rsvd5[8]; /* 0x130 */
28 unsigned int pllcmd; /* 0x138 */
29 unsigned int pllstat; /* 0x13c */
30 unsigned int alnctl; /* 0x140 */
31 unsigned int dchange; /* 0x144 */
32 unsigned int cken; /* 0x148 */
33 unsigned int ckstat; /* 0x14c */
34 unsigned int systat; /* 0x150 */
35 unsigned char rsvd6[12]; /* 0x154 */
36 unsigned int plldiv4; /* 0x160 */
37 unsigned int plldiv5; /* 0x164 */
38 unsigned int plldiv6; /* 0x168 */
39 unsigned int plldiv7; /* 0x16C */
40 unsigned int plldiv8; /* 0x170 */
41 unsigned int plldiv9; /* 0x174 */
42};
43
Heiko Schocher34061e82011-11-15 10:00:02 -0500[diff] [blame]44#define PLL_MASTER_LOCK (1 << 4)
45
46#define PLLCTL_CLOCK_MODE_SHIFT 8
Heiko Schocherf1084d62011-11-01 20:00:31 +0000[diff] [blame]47#define PLLCTL_PLLEN (1 << 0)
48#define PLLCTL_PLLPWRDN (1 << 1)
49#define PLLCTL_PLLRST (1 << 3)
Heiko Schocher34061e82011-11-15 10:00:02 -0500[diff] [blame]50#define PLLCTL_PLLDIS (1 << 4)
Heiko Schocherf1084d62011-11-01 20:00:31 +0000[diff] [blame]51#define PLLCTL_PLLENSRC (1 << 5)
52#define PLLCTL_RES_9 (1 << 8)
Heiko Schocher34061e82011-11-15 10:00:02 -0500[diff] [blame]53#define PLLCTL_EXTCLKSRC (1 << 9)
54
Ben Gardinerb2a47522012-01-16 07:43:15 +0000[diff] [blame]55#define PLL_DIVEN (1 << 15)
56#define PLL_POSTDEN PLL_DIVEN
Heiko Schocher34061e82011-11-15 10:00:02 -0500[diff] [blame]57
58#define PLL_SCSCFG3_DIV45PENA (1 << 2)
59#define PLL_SCSCFG3_EMA_CLKSRC (1 << 1)
60
61#define PLL_RSTYPE_POR (1 << 0)
62#define PLL_RSTYPE_XWRST (1 << 1)
Heiko Schocherf1084d62011-11-01 20:00:31 +0000[diff] [blame]63
64#define PLLSECCTL_TINITZ (1 << 16)
65#define PLLSECCTL_TENABLE (1 << 17)
66#define PLLSECCTL_TENABLEDIV (1 << 18)
67#define PLLSECCTL_STOPMODE (1 << 22)
68
69#define PLLCMD_GOSET (1 << 0)
Heiko Schocher34061e82011-11-15 10:00:02 -0500[diff] [blame]70#define PLLCMD_GOSTAT (1 << 0)
Heiko Schocherf1084d62011-11-01 20:00:31 +0000[diff] [blame]71
72#define PLL0_LOCK 0x07000000
73#define PLL1_LOCK 0x07000000
74
75#define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
76#define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
77
Heiko Schocher59214f82011-11-01 20:00:33 +0000[diff] [blame]78#define ARM_PLLDIV (offsetof(struct dv_pll_regs, plldiv2))
79#define DDR_PLLDIV (offsetof(struct dv_pll_regs, plldiv7))
Heiko Schocher109f5482011-11-01 20:00:34 +0000[diff] [blame]80#define SPI_PLLDIV (offsetof(struct dv_pll_regs, plldiv4))
Heiko Schocher59214f82011-11-01 20:00:33 +0000[diff] [blame]81
82unsigned int davinci_clk_get(unsigned int div);
Heiko Schocherf1084d62011-11-01 20:00:31 +0000[diff] [blame]83#endif /* _DV_PLL_DEFS_H_ */