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git01.mediatek.com / filogic / uboot / 4815f8eef133be616c6606912c2f6e660ad7426c / . / include / configs / bf548-ezkit.h
blob: c7b44ae427c69e276caa231862b98868856028ed [file] [log] [blame]
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]1/*
2 * U-boot - Configuration file for BF548 STAMP board
3 */
4
5#ifndef __CONFIG_BF548_EZKIT_H__
6#define __CONFIG_BF548_EZKIT_H__
7
Mike Frysinger18a407c2009-04-24 17:22:40 -0400[diff] [blame]8#include <asm/config-pre.h>
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]9
10
11/*
12 * Processor Settings
13 */
Mike Frysinger5b0c1282010-12-23 14:58:37 -0500[diff] [blame]14#define CONFIG_BFIN_CPU bf548-0.0
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 25000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 21
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 4
40
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_ADD_WDTH 10
46#define CONFIG_MEM_SIZE 64
47
48#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE
49#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222
50#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021
51
52/* Default EZ-Kit bank mapping:
53 * Async Bank 0 - 32MB Burst Flash
54 * Async Bank 1 - Ethernet
55 * Async Bank 2 - Nothing
56 * Async Bank 3 - Nothing
57 */
58#define CONFIG_EBIU_AMGCTL_VAL 0xFF
59#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
60#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
61#define CONFIG_EBIU_FCTL_VAL (BCLK_4)
62#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH)
63
Mike Frysingera2306572009-06-14 21:23:27 -0400[diff] [blame]64#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]65#define CONFIG_SYS_MALLOC_LEN (768 * 1024)
66
67
68/*
69 * Network Settings
70 */
71#define ADI_CMDS_NETWORK 1
Ben Warrenfbfdd3a2009-07-20 22:01:11 -0700[diff] [blame]72#define CONFIG_SMC911X 1
73#define CONFIG_SMC911X_BASE 0x24000000
74#define CONFIG_SMC911X_16_BIT
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]75#define CONFIG_HOSTNAME bf548-ezkit
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]76
77
78/*
79 * Flash Settings
80 */
81#define CONFIG_FLASH_CFI_DRIVER
82#define CONFIG_SYS_FLASH_BASE 0x20000000
83#define CONFIG_SYS_FLASH_CFI
84#define CONFIG_SYS_FLASH_PROTECTION
85#define CONFIG_SYS_MAX_FLASH_BANKS 1
86#define CONFIG_SYS_MAX_FLASH_SECT 259
87
88
89/*
90 * SPI Settings
91 */
92#define CONFIG_BFIN_SPI
93#define CONFIG_ENV_SPI_MAX_HZ 30000000
Mike Frysinger9a4406462009-06-14 22:29:35 -0400[diff] [blame]94#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]95#define CONFIG_SPI_FLASH_STMICRO
96
97
98/*
99 * Env Storage Settings
100 */
101#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
102#define CONFIG_ENV_IS_IN_SPI_FLASH
103#define CONFIG_ENV_OFFSET 0x10000
104#define CONFIG_ENV_SIZE 0x2000
105#define CONFIG_ENV_SECT_SIZE 0x10000
Mike Frysinger45b57bd2009-07-21 22:17:36 -0400[diff] [blame]106#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]107#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
108#define CONFIG_ENV_IS_IN_NAND
Mike Frysinger03ecad82011-03-17 17:07:47 -0400[diff] [blame]109#define CONFIG_ENV_OFFSET 0x60000
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]110#define CONFIG_ENV_SIZE 0x20000
111#else
Mike Frysingerba31b832011-05-09 15:43:27 -0400[diff] [blame]112/* The BF548-EZKIT uses a top boot flash */
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]113#define CONFIG_ENV_IS_IN_FLASH 1
Mike Frysingerba31b832011-05-09 15:43:27 -0400[diff] [blame]114#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
115#define CONFIG_ENV_OFFSET (0x1000000 - CONFIG_ENV_SECT_SIZE)
116#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
117#define CONFIG_ENV_SECT_SIZE 0x8000
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]118#endif
119
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]120/*
121 * NAND Settings
122 */
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]123#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
Bob Liuec39f222013-02-05 19:22:20 +0800[diff] [blame]124#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
125#define CONFIG_BFIN_NFC_BOOTROM_ECC
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]126#define CONFIG_DRIVER_NAND_BFIN
Bob Liuec39f222013-02-05 19:22:20 +0800[diff] [blame]127#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
128#define CONFIG_SYS_MAX_NAND_DEVICE 1
129#endif
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]130
131/*
132 * I2C Settings
133 */
Scott Jiang80d27fa2014-11-13 15:30:55 +0800[diff] [blame]134#define CONFIG_SYS_I2C
Scott Jiang655761e2014-11-13 15:30:53 +0800[diff] [blame]135#define CONFIG_SYS_I2C_ADI
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]136
137
138/*
139 * SATA
140 */
141#if !defined(__ADSPBF544__)
142#define CONFIG_LIBATA
143#define CONFIG_SYS_SATA_MAX_DEVICE 1
144#define CONFIG_LBA48
145#define CONFIG_PATA_BFIN
146#define CONFIG_BFIN_ATAPI_BASE_ADDR 0xFFC03800
147#define CONFIG_BFIN_ATA_MODE XFER_PIO_4
148#endif
149
150
151/*
152 * SDH Settings
153 */
154#if !defined(__ADSPBF544__)
Cliff Caie4638922009-11-20 08:24:43 +0000[diff] [blame]155#define CONFIG_GENERIC_MMC
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]156#define CONFIG_MMC
157#define CONFIG_BFIN_SDH
158#endif
159
160
161/*
162 * USB Settings
163 */
164#if !defined(__ADSPBF544__)
165#define CONFIG_USB
166#define CONFIG_MUSB_HCD
167#define CONFIG_USB_BLACKFIN
168#define CONFIG_USB_STORAGE
169#define CONFIG_MUSB_TIMEOUT 100000
170#endif
171
172
173/*
174 * Misc Settings
175 */
176#define CONFIG_BOARD_EARLY_INIT_F
Mike Frysingercc64ba62010-10-19 18:02:43 -0400[diff] [blame]177#define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 ))
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]178#define CONFIG_RTC_BFIN
179#define CONFIG_UART_CONSOLE 1
Mike Frysinger55c5d712010-09-29 20:24:16 +0000[diff] [blame]180#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]181
Sonic Zhang3edc3f32013-05-02 13:46:21 +0800[diff] [blame]182#define CONFIG_ADI_GPIO2
183
Bob Liuec39f222013-02-05 19:22:20 +0800[diff] [blame]184#undef CONFIG_VIDEO
185#ifdef CONFIG_VIDEO
186#define EASYLOGO_HEADER < asm/bfin_logo_230x230_gzip.h >
187#define CONFIG_DEB_DMA_URGENT
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]188#endif
189
190/* Define if want to do post memory test */
191#undef CONFIG_POST
192#ifdef CONFIG_POST
Mike Frysinger32ed1fe2011-05-10 16:22:25 -0400[diff] [blame]193#define CONFIG_POST_BSPEC1_GPIO_LEDS \
194 GPIO_PG6, GPIO_PG7, GPIO_PG8, GPIO_PG9, GPIO_PG10, GPIO_PG11,
195#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
196 GPIO_PB8, GPIO_PB9, GPIO_PB10, GPIO_PB11
197#define CONFIG_POST_BSPEC2_GPIO_NAMES \
198 13, 12, 11, 10,
Mike Frysinger368cfc82011-05-10 16:48:36 -0400[diff] [blame]199#define CONFIG_SYS_POST_FLASH_START 10
200#define CONFIG_SYS_POST_FLASH_END 127
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]201#endif
202
203
204/*
205 * Pull in common ADI header for remaining command/environment setup
206 */
207#include <configs/bfin_adi_common.h>
208
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]209#endif