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git01.mediatek.com / filogic / uboot / 4c77f064dc67f858c583222d4a6349b7db06e2bd / . / arch / m68k / cpu / mcf52x2 / start.S
blob: d48d0192eea2a95668c3c2374bebaf0c016ffbc7 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]2/*
3 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
4 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]5 */
6
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]7#include <asm-offsets.h>
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]8#include <config.h>
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]9#include <asm/cache.h>
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]10
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]11#define _START _start
12#define _FAULT _fault
13
14
15#define SAVE_ALL \
16 move.w #0x2700,%sr; /* disable intrs */ \
17 subl #60,%sp; /* space for 15 regs */ \
18 moveml %d0-%d7/%a0-%a6,%sp@; \
19
20#define RESTORE_ALL \
21 moveml %sp@,%d0-%d7/%a0-%a6; \
22 addl #60,%sp; /* space for 15 regs */ \
23 rte
24
25/* If we come from a pre-loader we don't need an initial exception
26 * table.
27 */
28#if !defined(CONFIG_MONITOR_IS_IN_RAM)
29
30.text
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]31
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]32/*
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]33 * Vector table. This is used for initial platform startup.
34 * These vectors are to catch any un-intended traps.
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]35 */
36_vectors:
Wolfgang Denkb4b1c462006-06-10 19:27:47 +0200[diff] [blame]37.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]38#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]39.long _start - CONFIG_TEXT_BASE
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]40#else
Wolfgang Denkb4b1c462006-06-10 19:27:47 +0200[diff] [blame]41.long _START
Zachary P. Landau0bba8622006-01-26 17:35:56 -0500[diff] [blame]42#endif
Wolfgang Denkb4b1c462006-06-10 19:27:47 +0200[diff] [blame]43
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]44.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
45.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
46.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
47.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
48.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
49.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
50.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
51.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
52
53.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
54.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
55.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
56.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
57.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
58.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
59.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
60.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
61
62.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
63.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
64.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
65.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
66.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
67.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70
71.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79
80#endif
81
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]82.text
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]83
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]84#if defined(CFG_SYS_INT_FLASH_BASE) && \
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]85 (defined(CONFIG_M5282) || defined(CONFIG_M5281))
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]86#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]87.long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
88.long 0xFFFFFFFF /* all sectors protected */
89.long 0x00000000 /* supervisor/User restriction */
90.long 0x00000000 /* programm/data space restriction */
91.long 0x00000000 /* Flash security */
92#endif
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]93#endif
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]94
95.globl _start
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]96_start:
97 nop
98 nop
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]99 move.w #0x2700,%sr
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]100
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]101#if defined(CONFIG_M5208)
102 /* Initialize RAMBAR: locate SRAM and validate it */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]103 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]104 movec %d0, %RAMBAR1
105#endif
106
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]107#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]108 /* set MBAR address + valid flag */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]109 move.l #(CFG_SYS_MBAR + 1), %d0
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]110 move.c %d0, %MBAR
111
stroese53395a22004-12-16 18:09:49 +0000[diff] [blame]112 /*** The 5249 has MBAR2 as well ***/
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]113#ifdef CFG_SYS_MBAR2
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]114 /* Get MBAR2 address */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]115 move.l #(CFG_SYS_MBAR2 + 1), %d0
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]116 /* Set MBAR2 */
117 movec %d0, #0xc0e
stroese53395a22004-12-16 18:09:49 +0000[diff] [blame]118#endif
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]119 move.l #(CFG_SYS_INIT_RAM_ADDR + 1), %d0
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]120 movec %d0, %RAMBAR0
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]121#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]122
Wolfgang Denkb4b1c462006-06-10 19:27:47 +0200[diff] [blame]123#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]124 /* set MBAR address + valid flag */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]125 move.l #(CFG_SYS_MBAR + 1), %d0
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]126 move.l %d0, 0x40000000
127
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]128 /* Initialize RAMBAR1: locate SRAM and validate it */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]129 move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]130 movec %d0, %RAMBAR1
131
Bartlomiej Sieka8ff81c62006-12-20 00:27:32 +0100[diff] [blame]132#if defined(CONFIG_M5282)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]133#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]134 /*
135 * Setup code in SRAM to initialize FLASHBAR,
136 * if start from internal Flash
137 */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]138 move.l #(_flashbar_setup-CFG_SYS_INT_FLASH_BASE), %a0
139 move.l #(_flashbar_setup_end-CFG_SYS_INT_FLASH_BASE), %a1
140 move.l #(CFG_SYS_INIT_RAM_ADDR), %a2
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]141_copy_flash:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]142 move.l (%a0)+, (%a2)+
143 cmp.l %a0, %a1
144 bgt.s _copy_flash
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]145 jmp CFG_SYS_INIT_RAM_ADDR
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]146
147_flashbar_setup:
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]148 /* Initialize FLASHBAR: locate internal Flash and validate it */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]149 move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0
TsiChung Liew7e5ae272008-03-13 14:26:32 -0500[diff] [blame]150 movec %d0, %FLASHBAR
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]151 jmp _after_flashbar_copy.L /* Force jump to absolute address */
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]152_flashbar_setup_end:
153 nop
154_after_flashbar_copy:
155#else
156 /* Setup code to initialize FLASHBAR, if start from external Memory */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]157 move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0
TsiChung Liewfcd4aac2008-08-11 15:54:25 +0000[diff] [blame]158 movec %d0, %FLASHBAR
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]159#endif /* (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) */
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]160
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]161#endif
Wolfgang Denk5b1657d2006-09-04 01:03:57 +0200[diff] [blame]162#endif
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]163 /*
164 * if we come from a pre-loader we have no exception table and
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]165 * therefore no VBR to set
166 */
167#if !defined(CONFIG_MONITOR_IS_IN_RAM)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]168#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
169 move.l #CFG_SYS_INT_FLASH_BASE, %d0
TsiChungLiew5bffcad2007-10-25 17:09:17 -0500[diff] [blame]170#else
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]171 move.l #CFG_SYS_FLASH_BASE, %d0
TsiChungLiew5bffcad2007-10-25 17:09:17 -0500[diff] [blame]172#endif
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]173 movec %d0, %VBR
Marian Balakowiczc20d87d2006-05-09 11:51:51 +0200[diff] [blame]174#endif
175
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]176#ifdef CONFIG_M5275
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]177 /* set MBAR address + valid flag */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]178 move.l #(CFG_SYS_MBAR + 1), %d0
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]179 move.l %d0, 0x40000000
180/* movec %d0, %MBAR */
181
182 /* Initialize RAMBAR: locate SRAM and validate it */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]183 move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]184 movec %d0, %RAMBAR1
185#endif
186
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]187 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]188 move.l #0, %d0
189 move.l #(ICACHE_STATUS), %a1 /* icache */
190 move.l #(DCACHE_STATUS), %a2 /* icache */
191 move.l %d0, (%a1)
192 move.l %d0, (%a2)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]193
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]194 /* put relocation table address to a5 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]195 move.l #__got_start, %a5
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]196
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]197 /* setup stack initially on top of internal static ram */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]198 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]199
200 /*
201 * if configured, malloc_f arena will be reserved first,
202 * then (and always) gd struct space will be reserved
203 */
204 move.l %sp, -(%sp)
205 move.l #board_init_f_alloc_reserve, %a1
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]206 jsr (%a1)
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]207
208 /* update stack and frame-pointers */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]209 move.l %d0, %sp
210 move.l %sp, %fp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]211
212 /* initialize reserved area */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]213 move.l %d0, -(%sp)
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]214 move.l #board_init_f_init_reserve, %a1
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]215 jsr (%a1)
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]216
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200[diff] [blame]217 /* run low-level CPU init code (from flash) */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]218 move.l #cpu_init_f, %a1
219 jsr (%a1)
220
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200[diff] [blame]221 /* run low-level board init code (from flash) */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]222 clr.l %sp@-
223 move.l #board_init_f, %a1
224 jsr (%a1)
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]225
Marian Balakowiczc20d87d2006-05-09 11:51:51 +0200[diff] [blame]226 /* board_init_f() does not return */
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]227
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]228/******************************************************************************/
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]229
230/*
Simon Glass284f71b2019-12-28 10:44:45 -0700[diff] [blame]231 * void relocate_code(addr_sp, gd, addr_moni)
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]232 *
233 * This "function" does not return, instead it continues in RAM
234 * after relocating the monitor code.
235 *
236 * r3 = dest
237 * r4 = src
238 * r5 = length in bytes
239 * r6 = cachelinesize
240 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]241.globl relocate_code
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]242relocate_code:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]243 link.w %a6,#0
244 move.l 8(%a6), %sp /* set new stack pointer */
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]245
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]246 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
247 move.l 16(%a6), %a0 /* Save copy of Destination Address */
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]248
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]249 move.l #CONFIG_SYS_MONITOR_BASE, %a1
250 move.l #__init_end, %a2
251 move.l %a0, %a3
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]252 /* copy the code to RAM */
2531:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]254 move.l (%a1)+, (%a3)+
255 cmp.l %a1,%a2
256 bgt.s 1b
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]257
258/*
259 * We are done. Do not return, instead branch to second part of board
260 * initialization, now running from RAM.
261 */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]262 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]263 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]264 jmp (%a1)
265
266in_ram:
267
268clear_bss:
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]269 /*
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]270 * Now clear BSS segment
271 */
272 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]273 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]274 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]275 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]2766:
277 clr.l (%a1)+
278 cmp.l %a1,%d1
279 bgt.s 6b
280
281 /*
282 * fix got table in RAM
283 */
284 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]285 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]286 move.l %a1,%a5 /* fix got pointer register a5 */
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]287
288 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]289 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]290
2917:
292 move.l (%a1),%d1
293 sub.l #_start,%d1
294 add.l %a0,%d1
295 move.l %d1,(%a1)+
296 cmp.l %a2, %a1
297 bne 7b
298
299 /* calculate relative jump to board_init_r in ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]300 move.l %a0, %a1
301 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]302
303 /* set parameters for board_init_r */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]304 move.l %a0,-(%sp) /* dest_addr */
305 move.l %d0,-(%sp) /* gd */
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]306 jsr (%a1)
307
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]308/******************************************************************************/
309
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]310/* exception code */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]311.globl _fault
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]312_fault:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]313 bra _fault
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]314
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]315.globl _exc_handler
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]316_exc_handler:
317 SAVE_ALL
318 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]319 bsr exc_handler
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]320 addql #4,%sp
321 RESTORE_ALL
322
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]323.globl _int_handler
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]324_int_handler:
325 SAVE_ALL
326 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]327 bsr int_handler
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]328 addql #4,%sp
329 RESTORE_ALL
330
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]331/******************************************************************************/
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]332
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]333.align 4