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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkf70cbb22004-02-23 20:48:38 +000020 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkc6097192002-11-03 00:24:07 +000021 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <clps7111.h>
wdenkc6097192002-11-03 00:24:07 +000031#include <asm/proc-armv/ptrace.h>
wdenkf2140d52004-07-01 16:30:44 +000032#include <asm/hardware.h>
wdenkc6097192002-11-03 00:24:07 +000033
wdenk2ebee312004-02-23 19:30:57 +000034#ifndef CONFIG_NETARM
wdenkc6097192002-11-03 00:24:07 +000035/* we always count down the max. */
36#define TIMER_LOAD_VAL 0xffff
wdenkc6097192002-11-03 00:24:07 +000037/* macro to read the 16 bit timer */
38#define READ_TIMER (IO_TC1D & 0xffff)
Gary Jennejohn7968bb52007-01-24 12:16:56 +010039
40#ifdef CONFIG_LPC2292
41#undef READ_TIMER
42#define READ_TIMER (0xFFFFFFFF - GET32(T0TC))
43#endif
44
wdenk2ebee312004-02-23 19:30:57 +000045#else
46#define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
wdenkf70cbb22004-02-23 20:48:38 +000047#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
48#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
wdenk2ebee312004-02-23 19:30:57 +000049#define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
50#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
51#endif
wdenkc6097192002-11-03 00:24:07 +000052
wdenk82db02f2004-07-11 22:19:26 +000053#ifdef CONFIG_S3C4510B
54/* require interrupts for the S3C4510B */
55# ifndef CONFIG_USE_IRQ
56# error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
57# else
58static struct _irq_handler IRQ_HANDLER[N_IRQS];
59# endif
60#endif /* CONFIG_S3C4510B */
61
wdenkc6097192002-11-03 00:24:07 +000062#ifdef CONFIG_USE_IRQ
63/* enable IRQ/FIQ interrupts */
64void enable_interrupts (void)
65{
66 unsigned long temp;
67 __asm__ __volatile__("mrs %0, cpsr\n"
68 "bic %0, %0, #0x80\n"
69 "msr cpsr_c, %0"
70 : "=r" (temp)
71 :
72 : "memory");
73}
74
75
76/*
77 * disable IRQ/FIQ interrupts
78 * returns true if interrupts had been enabled before we disabled them
79 */
80int disable_interrupts (void)
81{
82 unsigned long old,temp;
83 __asm__ __volatile__("mrs %0, cpsr\n"
84 "orr %1, %0, #0x80\n"
85 "msr cpsr_c, %1"
86 : "=r" (old), "=r" (temp)
87 :
88 : "memory");
89 return (old & 0x80) == 0;
90}
wdenk82db02f2004-07-11 22:19:26 +000091#else /* CONFIG_USE_IRQ */
wdenkc6097192002-11-03 00:24:07 +000092void enable_interrupts (void)
93{
94 return;
95}
96int disable_interrupts (void)
97{
98 return 0;
99}
100#endif
101
wdenkc6097192002-11-03 00:24:07 +0000102void bad_mode (void)
103{
104 panic ("Resetting CPU ...\n");
105 reset_cpu (0);
106}
107
108void show_regs (struct pt_regs *regs)
109{
110 unsigned long flags;
111 const char *processor_modes[] =
wdenk57b2d802003-06-27 21:31:46 +0000112 { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26",
wdenkc6097192002-11-03 00:24:07 +0000113"UK6_26", "UK7_26",
114 "UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26",
115 "UK14_26", "UK15_26",
116 "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32",
117 "UK6_32", "ABT_32",
118 "UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32",
119 "UK14_32", "SYS_32"
120 };
121
122 flags = condition_codes (regs);
123
wdenkf70cbb22004-02-23 20:48:38 +0000124 printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
125 "sp : %08lx ip : %08lx fp : %08lx\n",
wdenkc6097192002-11-03 00:24:07 +0000126 instruction_pointer (regs),
127 regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
wdenkf70cbb22004-02-23 20:48:38 +0000128 printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
wdenkc6097192002-11-03 00:24:07 +0000129 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
wdenkf70cbb22004-02-23 20:48:38 +0000130 printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
wdenkc6097192002-11-03 00:24:07 +0000131 regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
wdenkf70cbb22004-02-23 20:48:38 +0000132 printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
wdenkc6097192002-11-03 00:24:07 +0000133 regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
134 printf ("Flags: %c%c%c%c",
135 flags & CC_N_BIT ? 'N' : 'n',
136 flags & CC_Z_BIT ? 'Z' : 'z',
137 flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
138 printf (" IRQs %s FIQs %s Mode %s%s\n",
139 interrupts_enabled (regs) ? "on" : "off",
140 fast_interrupts_enabled (regs) ? "on" : "off",
141 processor_modes[processor_mode (regs)],
142 thumb_mode (regs) ? " (T)" : "");
143}
144
145void do_undefined_instruction (struct pt_regs *pt_regs)
146{
147 printf ("undefined instruction\n");
148 show_regs (pt_regs);
149 bad_mode ();
150}
151
152void do_software_interrupt (struct pt_regs *pt_regs)
153{
154 printf ("software interrupt\n");
155 show_regs (pt_regs);
156 bad_mode ();
157}
158
159void do_prefetch_abort (struct pt_regs *pt_regs)
160{
161 printf ("prefetch abort\n");
162 show_regs (pt_regs);
163 bad_mode ();
164}
165
166void do_data_abort (struct pt_regs *pt_regs)
167{
168 printf ("data abort\n");
169 show_regs (pt_regs);
170 bad_mode ();
171}
172
173void do_not_used (struct pt_regs *pt_regs)
174{
175 printf ("not used\n");
176 show_regs (pt_regs);
177 bad_mode ();
178}
179
180void do_fiq (struct pt_regs *pt_regs)
181{
182 printf ("fast interrupt request\n");
183 show_regs (pt_regs);
184 bad_mode ();
185}
186
187void do_irq (struct pt_regs *pt_regs)
188{
Wolfgang Denk4dc11462005-09-26 01:06:33 +0200189#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
wdenkc6097192002-11-03 00:24:07 +0000190 printf ("interrupt request\n");
191 show_regs (pt_regs);
192 bad_mode ();
wdenk82db02f2004-07-11 22:19:26 +0000193#elif defined(CONFIG_S3C4510B)
194 unsigned int pending;
195
196 while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */
197 IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
198
199 /* clear pending interrupt */
200 PUT_REG( REG_INTPEND, (1<<(pending>>2)));
201 }
Wolfgang Denk7f88a5e2005-10-06 17:08:18 +0200202#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
203 /* No do_irq() for IntegratorAP/CM720T as yet */
Gary Jennejohn7968bb52007-01-24 12:16:56 +0100204#elif defined(CONFIG_LPC2292)
205
206 void (*pfnct)(void);
207
208 pfnct = (void (*)(void))VICVectAddr;
209
210 (*pfnct)();
wdenk82db02f2004-07-11 22:19:26 +0000211#else
212#error do_irq() not defined for this CPU type
213#endif
214}
215
216
217#ifdef CONFIG_S3C4510B
218static void default_isr( void *data) {
219 printf ("default_isr(): called for IRQ %d\n", (int)data);
wdenkc6097192002-11-03 00:24:07 +0000220}
221
wdenk82db02f2004-07-11 22:19:26 +0000222static void timer_isr( void *data) {
223 unsigned int *pTime = (unsigned int *)data;
224
225 (*pTime)++;
226 if ( !(*pTime % (CFG_HZ/4))) {
227 /* toggle LED 0 */
228 PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
229 }
230
231}
232#endif
233
Wolfgang Denk7f88a5e2005-10-06 17:08:18 +0200234#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
235 /* Use IntegratorAP routines in board/integratorap.c */
236#else
237
Wolfgang Denk88bd7432005-10-09 00:22:48 +0200238static ulong timestamp;
239static ulong lastdec;
240
wdenkc6097192002-11-03 00:24:07 +0000241int interrupt_init (void)
242{
wdenkf2140d52004-07-01 16:30:44 +0000243
244#if defined(CONFIG_NETARM)
wdenkf70cbb22004-02-23 20:48:38 +0000245 /* disable all interrupts */
wdenk2ebee312004-02-23 19:30:57 +0000246 IRQEN = 0;
247
248 /* operate timer 2 in non-prescale mode */
249 TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CFG_HZ) |
250 NETARM_GEN_TCTL_ENABLE |
251 NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
252
253 /* set timer 2 counter */
254 lastdec = TIMER_LOAD_VAL;
Wolfgang Denk4dc11462005-09-26 01:06:33 +0200255#elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
wdenkc6097192002-11-03 00:24:07 +0000256 /* disable all interrupts */
257 IO_INTMR1 = 0;
258
259 /* operate timer 1 in prescale mode */
260 IO_SYSCON1 |= SYSCON1_TC1M;
261
262 /* select 2kHz clock source for timer 1 */
263 IO_SYSCON1 &= ~SYSCON1_TC1S;
264
265 /* set timer 1 counter */
266 lastdec = IO_TC1D = TIMER_LOAD_VAL;
wdenkf2140d52004-07-01 16:30:44 +0000267#elif defined(CONFIG_S3C4510B)
wdenk82db02f2004-07-11 22:19:26 +0000268 int i;
269
270 /* install default interrupt handlers */
271 for ( i = 0; i < N_IRQS; i++) {
272 IRQ_HANDLER[i].m_data = (void *)i;
273 IRQ_HANDLER[i].m_func = default_isr;
274 }
275
276 /* configure interrupts for IRQ mode */
277 PUT_REG( REG_INTMODE, 0x0);
278 /* clear any pending interrupts */
279 PUT_REG( REG_INTPEND, 0x1FFFFF);
280
wdenkf2140d52004-07-01 16:30:44 +0000281 lastdec = 0;
wdenk82db02f2004-07-11 22:19:26 +0000282
283 /* install interrupt handler for timer */
284 IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp;
285 IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
286
287 /* configure free running timer 0 */
288 PUT_REG( REG_TMOD, 0x0);
289 /* Stop timer 0 */
290 CLR_REG( REG_TMOD, TM0_RUN);
291
292 /* Configure for interval mode */
293 CLR_REG( REG_TMOD, TM1_TOGGLE);
294
295 /*
296 * Load Timer data register with count down value.
297 * count_down_val = CFG_SYS_CLK_FREQ/CFG_HZ
298 */
299 PUT_REG( REG_TDATA0, (CFG_SYS_CLK_FREQ / CFG_HZ));
300
301 /*
302 * Enable global interrupt
303 * Enable timer0 interrupt
304 */
305 CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
306
307 /* Start timer */
308 SET_REG( REG_TMOD, TM0_RUN);
Gary Jennejohn7968bb52007-01-24 12:16:56 +0100309#elif defined(CONFIG_LPC2292)
310 PUT32(T0IR, 0); /* disable all timer0 interrupts */
311 PUT32(T0TCR, 0); /* disable timer0 */
312 PUT32(T0PR, CFG_SYS_CLK_FREQ / CFG_HZ);
313 PUT32(T0MCR, 0);
314 PUT32(T0TC, 0);
315 PUT32(T0TCR, 1); /* enable timer0 */
wdenk82db02f2004-07-11 22:19:26 +0000316
wdenkf2140d52004-07-01 16:30:44 +0000317#else
318#error No interrupt_init() defined for this CPU type
wdenk2ebee312004-02-23 19:30:57 +0000319#endif
wdenkc6097192002-11-03 00:24:07 +0000320 timestamp = 0;
321
322 return (0);
323}
324
Wolfgang Denk7f88a5e2005-10-06 17:08:18 +0200325#endif /* ! IntegratorAP */
326
wdenkc6097192002-11-03 00:24:07 +0000327/*
328 * timer without interrupts
329 */
330
wdenkf2140d52004-07-01 16:30:44 +0000331
Gary Jennejohn7968bb52007-01-24 12:16:56 +0100332#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292)
wdenkf2140d52004-07-01 16:30:44 +0000333
wdenkc6097192002-11-03 00:24:07 +0000334void reset_timer (void)
335{
336 reset_timer_masked ();
337}
338
339ulong get_timer (ulong base)
340{
341 return get_timer_masked () - base;
342}
343
344void set_timer (ulong t)
345{
346 timestamp = t;
347}
348
349void udelay (unsigned long usec)
350{
351 ulong tmo;
352
353 tmo = usec / 1000;
354 tmo *= CFG_HZ;
355 tmo /= 1000;
356
357 tmo += get_timer (0);
358
359 while (get_timer_masked () < tmo)
Gary Jennejohn7968bb52007-01-24 12:16:56 +0100360#ifdef CONFIG_LPC2292
361 /* GJ - not sure whether this is really needed or a misunderstanding */
362 __asm__ __volatile__(" nop");
363#else
wdenkc6097192002-11-03 00:24:07 +0000364 /*NOP*/;
Gary Jennejohn7968bb52007-01-24 12:16:56 +0100365#endif
wdenkc6097192002-11-03 00:24:07 +0000366}
367
368void reset_timer_masked (void)
369{
370 /* reset time */
371 lastdec = READ_TIMER;
372 timestamp = 0;
373}
374
375ulong get_timer_masked (void)
376{
377 ulong now = READ_TIMER;
378
379 if (lastdec >= now) {
380 /* normal mode */
381 timestamp += lastdec - now;
382 } else {
383 /* we have an overflow ... */
384 timestamp += lastdec + TIMER_LOAD_VAL - now;
385 }
386 lastdec = now;
387
388 return timestamp;
389}
390
391void udelay_masked (unsigned long usec)
392{
393 ulong tmo;
wdenk7af1f9d2005-04-04 12:08:28 +0000394 ulong endtime;
395 signed long diff;
wdenkc6097192002-11-03 00:24:07 +0000396
wdenk7af1f9d2005-04-04 12:08:28 +0000397 if (usec >= 1000) {
398 tmo = usec / 1000;
399 tmo *= CFG_HZ;
400 tmo /= 1000;
401 } else {
402 tmo = usec * CFG_HZ;
403 tmo /= (1000*1000);
404 }
wdenkc6097192002-11-03 00:24:07 +0000405
wdenk7af1f9d2005-04-04 12:08:28 +0000406 endtime = get_timer_masked () + tmo;
wdenkc6097192002-11-03 00:24:07 +0000407
wdenk7af1f9d2005-04-04 12:08:28 +0000408 do {
409 ulong now = get_timer_masked ();
410 diff = endtime - now;
411 } while (diff >= 0);
wdenkc6097192002-11-03 00:24:07 +0000412}
wdenkf2140d52004-07-01 16:30:44 +0000413
414#elif defined(CONFIG_S3C4510B)
415
wdenk82db02f2004-07-11 22:19:26 +0000416ulong get_timer (ulong base)
417{
418 return timestamp - base;
419}
wdenkf2140d52004-07-01 16:30:44 +0000420
421void udelay (unsigned long usec)
422{
wdenk82db02f2004-07-11 22:19:26 +0000423 u32 ticks;
wdenkf2140d52004-07-01 16:30:44 +0000424
wdenk82db02f2004-07-11 22:19:26 +0000425 ticks = (usec * CFG_HZ) / 1000000;
wdenkf2140d52004-07-01 16:30:44 +0000426
wdenk82db02f2004-07-11 22:19:26 +0000427 ticks += get_timer (0);
wdenkf2140d52004-07-01 16:30:44 +0000428
wdenk82db02f2004-07-11 22:19:26 +0000429 while (get_timer (0) < ticks)
430 /*NOP*/;
wdenkf2140d52004-07-01 16:30:44 +0000431
wdenkf2140d52004-07-01 16:30:44 +0000432}
433
Wolfgang Denk7f88a5e2005-10-06 17:08:18 +0200434#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
435 /* No timer routines for IntegratorAP/CM720T as yet */
wdenkf2140d52004-07-01 16:30:44 +0000436#else
437#error Timer routines not defined for this CPU type
438#endif