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Chunhe Lan8e4f3ff2014-04-14 18:42:06 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __DDR_H__
8#define __DDR_H__
9struct board_specific_parameters {
10 u32 n_ranks;
11 u32 datarate_mhz_high;
12 u32 rank_gb;
13 u32 clk_adjust;
14 u32 wrlvl_start;
15 u32 wrlvl_ctl_2;
16 u32 wrlvl_ctl_3;
17};
18
19/*
20 * These tables contain all valid speeds we want to override with board
21 * specific parameters. datarate_mhz_high values need to be in ascending order
22 * for each n_ranks group.
23 */
24static const struct board_specific_parameters udimm0[] = {
25 /*
26 * memory controller 0
27 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
28 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
29 */
Shengzhou Liuf1510e62016-05-04 10:20:22 +080030 {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a},
31 {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09},
32 {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b},
33 {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a},
34 {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
35 {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
36 {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a},
37 {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a},
38 {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a},
39 {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b},
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080040 {}
41};
42
43static const struct board_specific_parameters rdimm0[] = {
44 /*
45 * memory controller 0
46 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
47 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
48 */
Shengzhou Liuf1510e62016-05-04 10:20:22 +080049 {4, 1350, 0, 10, 9, 0x08070605, 0x06070806},
50 {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906},
51 {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
52 {2, 1350, 0, 10, 9, 0x08070605, 0x06070806},
53 {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
54 {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
55 {1, 1350, 0, 10, 9, 0x08070605, 0x06070806},
56 {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
57 {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07},
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080058 {}
59};
60
61/*
62 * The three slots have slightly different timing. The center values are good
63 * for all slots. We use identical speed tables for them. In future use, if
64 * DIMMs require separated tables, make more entries as needed.
65 */
66static const struct board_specific_parameters *udimms[] = {
67 udimm0,
68};
69
70/*
71 * The three slots have slightly different timing. See comments above.
72 */
73static const struct board_specific_parameters *rdimms[] = {
74 rdimm0,
75};
76
77
78#endif