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git01.mediatek.com / filogic / uboot / f1264ba094e0f91f65f08624f892383fe7e8bc61 / . / arch / arm / dts / zynqmp-zcu106-revA.dts
blob: 7a8094a16b79869f5f545378aba97f9aee9d867b [file] [log] [blame]
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU106
4 *
Michal Simek821e32a2021-05-31 09:50:01 +0200[diff] [blame]5 * (C) Copyright 2016 - 2021, Xilinx, Inc.
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]6 *
Michal Simeka8c94362023-07-10 14:35:49 +0200[diff] [blame]7 * Michal Simek <michal.simek@amd.com>
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]17#include <dt-bindings/phy/phy.h>
18
19/ {
20 model = "ZynqMP ZCU106 RevA";
21 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
22
23 aliases {
24 ethernet0 = &gem3;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 mmc0 = &sdhci1;
Michal Simek53b145d2021-06-03 11:46:50 +0200[diff] [blame]28 nvmem0 = &eeprom;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]29 rtc0 = &rtc;
30 serial0 = &uart0;
31 serial1 = &uart1;
32 serial2 = &dcc;
33 spi0 = &qspi;
34 usb0 = &usb0;
35 };
36
37 chosen {
38 bootargs = "earlycon";
39 stdout-path = "serial0:115200n8";
40 };
41
42 memory@0 {
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
45 };
46
47 gpio-keys {
48 compatible = "gpio-keys";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]49 autorepeat;
Michal Simek192d4ae2022-12-09 13:56:40 +0100[diff] [blame]50 switch-19 {
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]51 label = "sw19";
52 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
53 linux,code = <KEY_DOWN>;
Sudeep Holla13104ce2018-10-24 12:45:40 +0100[diff] [blame]54 wakeup-source;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]55 autorepeat;
56 };
57 };
58
59 leds {
60 compatible = "gpio-leds";
Michal Simek2ef53362018-11-08 10:06:53 +0100[diff] [blame]61 heartbeat-led {
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]62 label = "heartbeat";
63 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
64 linux,default-trigger = "heartbeat";
65 };
66 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]67
68 ina226-u76 {
69 compatible = "iio-hwmon";
70 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
71 };
72 ina226-u77 {
73 compatible = "iio-hwmon";
74 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
75 };
76 ina226-u78 {
77 compatible = "iio-hwmon";
78 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
79 };
80 ina226-u87 {
81 compatible = "iio-hwmon";
82 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
83 };
84 ina226-u85 {
85 compatible = "iio-hwmon";
86 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
87 };
88 ina226-u86 {
89 compatible = "iio-hwmon";
90 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
91 };
92 ina226-u93 {
93 compatible = "iio-hwmon";
94 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
95 };
96 ina226-u88 {
97 compatible = "iio-hwmon";
98 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
99 };
100 ina226-u15 {
101 compatible = "iio-hwmon";
102 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
103 };
104 ina226-u92 {
105 compatible = "iio-hwmon";
106 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
107 };
108 ina226-u79 {
109 compatible = "iio-hwmon";
110 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
111 };
112 ina226-u81 {
113 compatible = "iio-hwmon";
114 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
115 };
116 ina226-u80 {
117 compatible = "iio-hwmon";
118 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
119 };
120 ina226-u84 {
121 compatible = "iio-hwmon";
122 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
123 };
124 ina226-u16 {
125 compatible = "iio-hwmon";
126 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
127 };
128 ina226-u65 {
129 compatible = "iio-hwmon";
130 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
131 };
132 ina226-u74 {
133 compatible = "iio-hwmon";
134 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
135 };
136 ina226-u75 {
137 compatible = "iio-hwmon";
138 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
139 };
Michal Simek958c0e92020-11-26 14:25:02 +0100[diff] [blame]140
141 /* 48MHz reference crystal */
142 ref48: ref48M {
143 compatible = "fixed-clock";
144 #clock-cells = <0>;
145 clock-frequency = <48000000>;
146 };
147
148 refhdmi: refhdmi {
149 compatible = "fixed-clock";
150 #clock-cells = <0>;
151 clock-frequency = <114285000>;
152 };
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]153};
154
155&can1 {
156 status = "okay";
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_can1_default>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]159};
160
161&dcc {
162 status = "okay";
Michal Simek958c0e92020-11-26 14:25:02 +0100[diff] [blame]163};
164
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]165&fpd_dma_chan1 {
166 status = "okay";
167};
168
169&fpd_dma_chan2 {
170 status = "okay";
171};
172
173&fpd_dma_chan3 {
174 status = "okay";
175};
176
177&fpd_dma_chan4 {
178 status = "okay";
179};
180
181&fpd_dma_chan5 {
182 status = "okay";
183};
184
185&fpd_dma_chan6 {
186 status = "okay";
187};
188
189&fpd_dma_chan7 {
190 status = "okay";
191};
192
193&fpd_dma_chan8 {
194 status = "okay";
195};
196
197&gem3 {
198 status = "okay";
199 phy-handle = <&phy0>;
200 phy-mode = "rgmii-id";
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_gem3_default>;
Michal Simek62b5cfc2022-11-16 11:59:19 +0100[diff] [blame]203 mdio: mdio {
204 #address-cells = <1>;
205 #size-cells = <0>;
206 phy0: ethernet-phy@c {
207 #phy-cells = <1>;
208 reg = <0xc>;
209 compatible = "ethernet-phy-id2000.a231";
210 ti,rx-internal-delay = <0x8>;
211 ti,tx-internal-delay = <0xa>;
212 ti,fifo-depth = <0x1>;
213 ti,dp83867-rxctrl-strap-quirk;
214 reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
215 };
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]216 };
217};
218
219&gpio {
220 status = "okay";
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_gpio_default>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]223};
224
225&gpu {
226 status = "okay";
227};
228
229&i2c0 {
230 status = "okay";
231 clock-frequency = <400000>;
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]232 pinctrl-names = "default", "gpio";
233 pinctrl-0 = <&pinctrl_i2c0_default>;
234 pinctrl-1 = <&pinctrl_i2c0_gpio>;
Manikanta Guntupallicc45c9c2023-07-10 14:37:28 +0200[diff] [blame]235 scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
236 sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]237
238 tca6416_u97: gpio@20 {
239 compatible = "ti,tca6416";
240 reg = <0x20>;
241 gpio-controller; /* interrupt not connected */
242 #gpio-cells = <2>;
243 /*
244 * IRQ not connected
245 * Lines:
246 * 0 - SFP_SI5328_INT_ALM
247 * 1 - HDMI_SI5328_INT_ALM
248 * 5 - IIC_MUX_RESET_B
249 * 6 - GEM3_EXP_RESET_B
250 * 10 - FMC_HPC0_PRSNT_M2C_B
251 * 11 - FMC_HPC1_PRSNT_M2C_B
252 * 2-4, 7, 12-17 - not connected
253 */
254 };
255
256 tca6416_u61: gpio@21 {
257 compatible = "ti,tca6416";
258 reg = <0x21>;
259 gpio-controller;
260 #gpio-cells = <2>;
261 /*
262 * IRQ not connected
263 * Lines:
264 * 0 - VCCPSPLL_EN
265 * 1 - MGTRAVCC_EN
266 * 2 - MGTRAVTT_EN
267 * 3 - VCCPSDDRPLL_EN
268 * 4 - MIO26_PMU_INPUT_LS
269 * 5 - PL_PMBUS_ALERT
270 * 6 - PS_PMBUS_ALERT
271 * 7 - MAXIM_PMBUS_ALERT
272 * 10 - PL_DDR4_VTERM_EN
273 * 11 - PL_DDR4_VPP_2V5_EN
274 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
275 * 13 - PS_DIMM_SUSPEND_EN
276 * 14 - PS_DDR4_VTERM_EN
277 * 15 - PS_DDR4_VPP_2V5_EN
278 * 16 - 17 - not connected
279 */
280 };
281
282 i2c-mux@75 { /* u60 */
283 compatible = "nxp,pca9544";
284 #address-cells = <1>;
285 #size-cells = <0>;
286 reg = <0x75>;
287 i2c@0 {
288 #address-cells = <1>;
289 #size-cells = <0>;
290 reg = <0>;
291 /* PS_PMBUS */
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]292 u76: ina226@40 { /* u76 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]293 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]294 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]295 label = "ina226-u76";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]296 reg = <0x40>;
297 shunt-resistor = <5000>;
298 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]299 u77: ina226@41 { /* u77 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]300 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]301 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]302 label = "ina226-u77";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]303 reg = <0x41>;
304 shunt-resistor = <5000>;
305 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]306 u78: ina226@42 { /* u78 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]307 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]308 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]309 label = "ina226-u78";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]310 reg = <0x42>;
311 shunt-resistor = <5000>;
312 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]313 u87: ina226@43 { /* u87 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]314 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]315 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]316 label = "ina226-u87";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]317 reg = <0x43>;
318 shunt-resistor = <5000>;
319 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]320 u85: ina226@44 { /* u85 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]321 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]322 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]323 label = "ina226-u85";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]324 reg = <0x44>;
325 shunt-resistor = <5000>;
326 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]327 u86: ina226@45 { /* u86 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]328 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]329 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]330 label = "ina226-u86";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]331 reg = <0x45>;
332 shunt-resistor = <5000>;
333 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]334 u93: ina226@46 { /* u93 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]335 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]336 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]337 label = "ina226-u93";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]338 reg = <0x46>;
339 shunt-resistor = <5000>;
340 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]341 u88: ina226@47 { /* u88 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]342 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]343 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]344 label = "ina226-u88";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]345 reg = <0x47>;
346 shunt-resistor = <5000>;
347 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]348 u15: ina226@4a { /* u15 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]349 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]350 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]351 label = "ina226-u15";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]352 reg = <0x4a>;
353 shunt-resistor = <5000>;
354 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]355 u92: ina226@4b { /* u92 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]356 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]357 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]358 label = "ina226-u92";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]359 reg = <0x4b>;
360 shunt-resistor = <5000>;
361 };
362 };
363 i2c@1 {
364 #address-cells = <1>;
365 #size-cells = <0>;
366 reg = <1>;
367 /* PL_PMBUS */
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]368 u79: ina226@40 { /* u79 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]369 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]370 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]371 label = "ina226-u79";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]372 reg = <0x40>;
373 shunt-resistor = <2000>;
374 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]375 u81: ina226@41 { /* u81 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]376 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]377 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]378 label = "ina226-u81";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]379 reg = <0x41>;
380 shunt-resistor = <5000>;
381 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]382 u80: ina226@42 { /* u80 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]383 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]384 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]385 label = "ina226-u80";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]386 reg = <0x42>;
387 shunt-resistor = <5000>;
388 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]389 u84: ina226@43 { /* u84 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]390 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]391 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]392 label = "ina226-u84";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]393 reg = <0x43>;
394 shunt-resistor = <5000>;
395 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]396 u16: ina226@44 { /* u16 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]397 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]398 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]399 label = "ina226-u16";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]400 reg = <0x44>;
401 shunt-resistor = <5000>;
402 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]403 u65: ina226@45 { /* u65 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]404 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]405 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]406 label = "ina226-u65";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]407 reg = <0x45>;
408 shunt-resistor = <5000>;
409 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]410 u74: ina226@46 { /* u74 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]411 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]412 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]413 label = "ina226-u74";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]414 reg = <0x46>;
415 shunt-resistor = <5000>;
416 };
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]417 u75: ina226@47 { /* u75 */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]418 compatible = "ti,ina226";
Michal Simek2ec41ef2019-08-26 09:46:36 +0200[diff] [blame]419 #io-channel-cells = <1>;
Michal Simek9df54d12019-08-26 10:18:13 +0200[diff] [blame]420 label = "ina226-u75";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]421 reg = <0x47>;
422 shunt-resistor = <5000>;
423 };
424 };
425 i2c@2 {
426 #address-cells = <1>;
427 #size-cells = <0>;
428 reg = <2>;
429 /* MAXIM_PMBUS - 00 */
430 max15301@a { /* u46 */
431 compatible = "maxim,max15301";
432 reg = <0xa>;
433 };
434 max15303@b { /* u4 */
435 compatible = "maxim,max15303";
436 reg = <0xb>;
437 };
438 max15303@10 { /* u13 */
439 compatible = "maxim,max15303";
440 reg = <0x10>;
441 };
442 max15301@13 { /* u47 */
443 compatible = "maxim,max15301";
444 reg = <0x13>;
445 };
446 max15303@14 { /* u7 */
447 compatible = "maxim,max15303";
448 reg = <0x14>;
449 };
450 max15303@15 { /* u6 */
451 compatible = "maxim,max15303";
452 reg = <0x15>;
453 };
454 max15303@16 { /* u10 */
455 compatible = "maxim,max15303";
456 reg = <0x16>;
457 };
458 max15303@17 { /* u9 */
459 compatible = "maxim,max15303";
460 reg = <0x17>;
461 };
462 max15301@18 { /* u63 */
463 compatible = "maxim,max15301";
464 reg = <0x18>;
465 };
466 max15303@1a { /* u49 */
467 compatible = "maxim,max15303";
468 reg = <0x1a>;
469 };
470 max15303@1b { /* u8 */
471 compatible = "maxim,max15303";
472 reg = <0x1b>;
473 };
474 max15303@1d { /* u18 */
475 compatible = "maxim,max15303";
476 reg = <0x1d>;
477 };
478
479 max20751@72 { /* u95 */
480 compatible = "maxim,max20751";
481 reg = <0x72>;
482 };
483 max20751@73 { /* u96 */
484 compatible = "maxim,max20751";
485 reg = <0x73>;
486 };
487 };
488 /* Bus 3 is not connected */
489 };
490};
491
492&i2c1 {
493 status = "okay";
494 clock-frequency = <400000>;
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]495 pinctrl-names = "default", "gpio";
496 pinctrl-0 = <&pinctrl_i2c1_default>;
497 pinctrl-1 = <&pinctrl_i2c1_gpio>;
Manikanta Guntupallicc45c9c2023-07-10 14:37:28 +0200[diff] [blame]498 scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
499 sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]500
501 /* PL i2c via PCA9306 - u45 */
502 i2c-mux@74 { /* u34 */
503 compatible = "nxp,pca9548";
504 #address-cells = <1>;
505 #size-cells = <0>;
506 reg = <0x74>;
507 i2c@0 {
508 #address-cells = <1>;
509 #size-cells = <0>;
510 reg = <0>;
511 /*
512 * IIC_EEPROM 1kB memory which uses 256B blocks
513 * where every block has different address.
514 * 0 - 256B address 0x54
515 * 256B - 512B address 0x55
516 * 512B - 768B address 0x56
517 * 768B - 1024B address 0x57
518 */
519 eeprom: eeprom@54 { /* u23 */
520 compatible = "atmel,24c08";
521 reg = <0x54>;
522 };
523 };
524 i2c@1 {
525 #address-cells = <1>;
526 #size-cells = <0>;
527 reg = <1>;
528 si5341: clock-generator@36 { /* SI5341 - u69 */
Michal Simek958c0e92020-11-26 14:25:02 +0100[diff] [blame]529 compatible = "silabs,si5341";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]530 reg = <0x36>;
Michal Simek958c0e92020-11-26 14:25:02 +0100[diff] [blame]531 #clock-cells = <2>;
532 #address-cells = <1>;
533 #size-cells = <0>;
534 clocks = <&ref48>;
535 clock-names = "xtal";
536 clock-output-names = "si5341";
537
538 si5341_0: out@0 {
539 /* refclk0 for PS-GT, used for DP */
540 reg = <0>;
541 always-on;
542 };
543 si5341_2: out@2 {
544 /* refclk2 for PS-GT, used for USB3 */
545 reg = <2>;
546 always-on;
547 };
548 si5341_3: out@3 {
549 /* refclk3 for PS-GT, used for SATA */
550 reg = <3>;
551 always-on;
552 };
553 si5341_6: out@6 {
554 /* refclk6 PL CLK125 */
555 reg = <6>;
556 always-on;
557 };
558 si5341_7: out@7 {
559 /* refclk7 PL CLK74 */
560 reg = <7>;
561 always-on;
562 };
563 si5341_9: out@9 {
564 /* refclk9 used for PS_REF_CLK 33.3 MHz */
565 reg = <9>;
566 always-on;
567 };
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]568 };
569
570 };
571 i2c@2 {
572 #address-cells = <1>;
573 #size-cells = <0>;
574 reg = <2>;
575 si570_1: clock-generator@5d { /* USER SI570 - u42 */
576 #clock-cells = <0>;
577 compatible = "silabs,si570";
578 reg = <0x5d>;
579 temperature-stability = <50>;
580 factory-fout = <300000000>;
581 clock-frequency = <300000000>;
Michal Simek3cf07bf2018-07-18 12:10:02 +0200[diff] [blame]582 clock-output-names = "si570_user";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]583 };
584 };
585 i2c@3 {
586 #address-cells = <1>;
587 #size-cells = <0>;
588 reg = <3>;
589 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
590 #clock-cells = <0>;
591 compatible = "silabs,si570";
592 reg = <0x5d>;
593 temperature-stability = <50>; /* copy from zc702 */
594 factory-fout = <156250000>;
595 clock-frequency = <148500000>;
Michal Simek3cf07bf2018-07-18 12:10:02 +0200[diff] [blame]596 clock-output-names = "si570_mgt";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]597 };
598 };
599 i2c@4 {
600 #address-cells = <1>;
601 #size-cells = <0>;
602 reg = <4>;
Michal Simek345508b2022-05-11 11:52:54 +0200[diff] [blame]603 si5328: clock-generator@69 {/* SI5328 - u20 */
604 compatible = "silabs,si5328";
605 reg = <0x69>;
606 /*
607 * Chip has interrupt present connected to PL
608 * interrupt-parent = <&>;
609 * interrupts = <>;
610 */
611 #address-cells = <1>;
612 #size-cells = <0>;
613 #clock-cells = <1>;
614 clocks = <&refhdmi>;
615 clock-names = "xtal";
616 clock-output-names = "si5328";
617
618 si5328_clk: clk0@0 {
619 reg = <0>;
620 clock-frequency = <27000000>;
621 };
622 };
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]623 };
624 i2c@5 {
625 #address-cells = <1>;
626 #size-cells = <0>;
627 reg = <5>; /* FAN controller */
628 temp@4c {/* lm96163 - u128 */
629 compatible = "national,lm96163";
630 reg = <0x4c>;
631 };
632 };
633 /* 6 - 7 unconnected */
634 };
635
636 i2c-mux@75 {
637 compatible = "nxp,pca9548"; /* u135 */
638 #address-cells = <1>;
639 #size-cells = <0>;
640 reg = <0x75>;
641
642 i2c@0 {
643 #address-cells = <1>;
644 #size-cells = <0>;
645 reg = <0>;
646 /* HPC0_IIC */
647 };
648 i2c@1 {
649 #address-cells = <1>;
650 #size-cells = <0>;
651 reg = <1>;
652 /* HPC1_IIC */
653 };
654 i2c@2 {
655 #address-cells = <1>;
656 #size-cells = <0>;
657 reg = <2>;
658 /* SYSMON */
659 };
660 i2c@3 {
661 #address-cells = <1>;
662 #size-cells = <0>;
663 reg = <3>;
664 /* DDR4 SODIMM */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]665 };
666 i2c@4 {
667 #address-cells = <1>;
668 #size-cells = <0>;
669 reg = <4>;
670 /* SEP 3 */
671 };
672 i2c@5 {
673 #address-cells = <1>;
674 #size-cells = <0>;
675 reg = <5>;
676 /* SEP 2 */
677 };
678 i2c@6 {
679 #address-cells = <1>;
680 #size-cells = <0>;
681 reg = <6>;
682 /* SEP 1 */
683 };
684 i2c@7 {
685 #address-cells = <1>;
686 #size-cells = <0>;
687 reg = <7>;
688 /* SEP 0 */
689 };
690 };
691};
692
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]693&pinctrl0 {
694 status = "okay";
695 pinctrl_i2c0_default: i2c0-default {
696 mux {
697 groups = "i2c0_3_grp";
698 function = "i2c0";
699 };
700
701 conf {
702 groups = "i2c0_3_grp";
703 bias-pull-up;
704 slew-rate = <SLEW_RATE_SLOW>;
705 power-source = <IO_STANDARD_LVCMOS18>;
706 };
707 };
708
709 pinctrl_i2c0_gpio: i2c0-gpio {
710 mux {
711 groups = "gpio0_14_grp", "gpio0_15_grp";
712 function = "gpio0";
713 };
714
715 conf {
716 groups = "gpio0_14_grp", "gpio0_15_grp";
717 slew-rate = <SLEW_RATE_SLOW>;
718 power-source = <IO_STANDARD_LVCMOS18>;
719 };
720 };
721
722 pinctrl_i2c1_default: i2c1-default {
723 mux {
724 groups = "i2c1_4_grp";
725 function = "i2c1";
726 };
727
728 conf {
729 groups = "i2c1_4_grp";
730 bias-pull-up;
731 slew-rate = <SLEW_RATE_SLOW>;
732 power-source = <IO_STANDARD_LVCMOS18>;
733 };
734 };
735
736 pinctrl_i2c1_gpio: i2c1-gpio {
737 mux {
738 groups = "gpio0_16_grp", "gpio0_17_grp";
739 function = "gpio0";
740 };
741
742 conf {
743 groups = "gpio0_16_grp", "gpio0_17_grp";
744 slew-rate = <SLEW_RATE_SLOW>;
745 power-source = <IO_STANDARD_LVCMOS18>;
746 };
747 };
748
749 pinctrl_uart0_default: uart0-default {
750 mux {
751 groups = "uart0_4_grp";
752 function = "uart0";
753 };
754
755 conf {
756 groups = "uart0_4_grp";
757 slew-rate = <SLEW_RATE_SLOW>;
758 power-source = <IO_STANDARD_LVCMOS18>;
759 };
760
761 conf-rx {
762 pins = "MIO18";
763 bias-high-impedance;
764 };
765
766 conf-tx {
767 pins = "MIO19";
768 bias-disable;
769 };
770 };
771
772 pinctrl_uart1_default: uart1-default {
773 mux {
774 groups = "uart1_5_grp";
775 function = "uart1";
776 };
777
778 conf {
779 groups = "uart1_5_grp";
780 slew-rate = <SLEW_RATE_SLOW>;
781 power-source = <IO_STANDARD_LVCMOS18>;
782 };
783
784 conf-rx {
785 pins = "MIO21";
786 bias-high-impedance;
787 };
788
789 conf-tx {
790 pins = "MIO20";
791 bias-disable;
792 };
793 };
794
795 pinctrl_usb0_default: usb0-default {
796 mux {
797 groups = "usb0_0_grp";
798 function = "usb0";
799 };
800
801 conf {
802 groups = "usb0_0_grp";
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]803 power-source = <IO_STANDARD_LVCMOS18>;
804 };
805
806 conf-rx {
807 pins = "MIO52", "MIO53", "MIO55";
808 bias-high-impedance;
Ashok Reddy Soma4d0ecf62022-06-15 12:16:13 +0200[diff] [blame]809 drive-strength = <12>;
810 slew-rate = <SLEW_RATE_FAST>;
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]811 };
812
813 conf-tx {
814 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
815 "MIO60", "MIO61", "MIO62", "MIO63";
816 bias-disable;
Ashok Reddy Soma4d0ecf62022-06-15 12:16:13 +0200[diff] [blame]817 drive-strength = <4>;
818 slew-rate = <SLEW_RATE_SLOW>;
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]819 };
820 };
821
822 pinctrl_gem3_default: gem3-default {
823 mux {
824 function = "ethernet3";
825 groups = "ethernet3_0_grp";
826 };
827
828 conf {
829 groups = "ethernet3_0_grp";
830 slew-rate = <SLEW_RATE_SLOW>;
831 power-source = <IO_STANDARD_LVCMOS18>;
832 };
833
834 conf-rx {
835 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
836 "MIO75";
837 bias-high-impedance;
838 low-power-disable;
839 };
840
841 conf-tx {
842 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
843 "MIO69";
844 bias-disable;
845 low-power-enable;
846 };
847
848 mux-mdio {
849 function = "mdio3";
850 groups = "mdio3_0_grp";
851 };
852
853 conf-mdio {
854 groups = "mdio3_0_grp";
855 slew-rate = <SLEW_RATE_SLOW>;
856 power-source = <IO_STANDARD_LVCMOS18>;
857 bias-disable;
858 };
859 };
860
861 pinctrl_can1_default: can1-default {
862 mux {
863 function = "can1";
864 groups = "can1_6_grp";
865 };
866
867 conf {
868 groups = "can1_6_grp";
869 slew-rate = <SLEW_RATE_SLOW>;
870 power-source = <IO_STANDARD_LVCMOS18>;
871 };
872
873 conf-rx {
874 pins = "MIO25";
875 bias-high-impedance;
876 };
877
878 conf-tx {
879 pins = "MIO24";
880 bias-disable;
881 };
882 };
883
884 pinctrl_sdhci1_default: sdhci1-default {
885 mux {
886 groups = "sdio1_0_grp";
887 function = "sdio1";
888 };
889
890 conf {
891 groups = "sdio1_0_grp";
892 slew-rate = <SLEW_RATE_SLOW>;
893 power-source = <IO_STANDARD_LVCMOS18>;
894 bias-disable;
895 };
896
897 mux-cd {
898 groups = "sdio1_cd_0_grp";
899 function = "sdio1_cd";
900 };
901
902 conf-cd {
903 groups = "sdio1_cd_0_grp";
904 bias-high-impedance;
905 bias-pull-up;
906 slew-rate = <SLEW_RATE_SLOW>;
907 power-source = <IO_STANDARD_LVCMOS18>;
908 };
909
910 mux-wp {
911 groups = "sdio1_wp_0_grp";
912 function = "sdio1_wp";
913 };
914
915 conf-wp {
916 groups = "sdio1_wp_0_grp";
917 bias-high-impedance;
918 bias-pull-up;
919 slew-rate = <SLEW_RATE_SLOW>;
920 power-source = <IO_STANDARD_LVCMOS18>;
921 };
922 };
923
924 pinctrl_gpio_default: gpio-default {
925 mux {
926 function = "gpio0";
927 groups = "gpio0_22_grp", "gpio0_23_grp";
928 };
929
930 conf {
931 groups = "gpio0_22_grp", "gpio0_23_grp";
932 slew-rate = <SLEW_RATE_SLOW>;
933 power-source = <IO_STANDARD_LVCMOS18>;
934 };
935
936 mux-msp {
937 function = "gpio0";
938 groups = "gpio0_13_grp", "gpio0_38_grp";
939 };
940
941 conf-msp {
942 groups = "gpio0_13_grp", "gpio0_38_grp";
943 slew-rate = <SLEW_RATE_SLOW>;
944 power-source = <IO_STANDARD_LVCMOS18>;
945 };
946
947 conf-pull-up {
948 pins = "MIO22";
949 bias-pull-up;
950 };
951
952 conf-pull-none {
953 pins = "MIO13", "MIO23", "MIO38";
954 bias-disable;
955 };
956 };
957};
958
Michal Simek93a89f32021-06-01 16:42:50 +0200[diff] [blame]959&psgtr {
960 status = "okay";
961 /* nc, sata, usb3, dp */
962 clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
963 clock-names = "ref1", "ref2", "ref3";
964};
965
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]966&qspi {
967 status = "okay";
968 is-dual = <1>;
969 flash@0 {
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]970 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]971 #address-cells = <1>;
972 #size-cells = <1>;
973 reg = <0x0>;
Amit Kumar Mahapatraa02408b2022-05-10 16:33:01 +0200[diff] [blame]974 spi-tx-bus-width = <4>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]975 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
976 spi-max-frequency = <108000000>; /* Based on DC1 spec */
Michal Simek70fafdf2020-02-14 14:19:56 +0100[diff] [blame]977 partition@0 { /* for testing purpose */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]978 label = "qspi-fsbl-uboot";
979 reg = <0x0 0x100000>;
980 };
Michal Simek70fafdf2020-02-14 14:19:56 +0100[diff] [blame]981 partition@100000 { /* for testing purpose */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]982 label = "qspi-linux";
983 reg = <0x100000 0x500000>;
984 };
Michal Simek70fafdf2020-02-14 14:19:56 +0100[diff] [blame]985 partition@600000 { /* for testing purpose */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]986 label = "qspi-device-tree";
987 reg = <0x600000 0x20000>;
988 };
Michal Simek70fafdf2020-02-14 14:19:56 +0100[diff] [blame]989 partition@620000 { /* for testing purpose */
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]990 label = "qspi-rootfs";
991 reg = <0x620000 0x5E0000>;
992 };
993 };
994};
995
996&rtc {
997 status = "okay";
998};
999
1000&sata {
1001 status = "okay";
1002 /* SATA OOB timing settings */
1003 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
1004 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
1005 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
1006 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
1007 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
1008 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
1009 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
1010 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
1011 phy-names = "sata-phy";
Michal Simek958c0e92020-11-26 14:25:02 +0100[diff] [blame]1012 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]1013};
1014
1015/* SD1 with level shifter */
1016&sdhci1 {
1017 status = "okay";
Manish Naranie2ba0932020-02-13 23:37:30 -0700[diff] [blame]1018 /*
1019 * This property should be removed for supporting UHS mode
1020 */
1021 no-1-8-v;
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]1022 pinctrl-names = "default";
1023 pinctrl-0 = <&pinctrl_sdhci1_default>;
Michal Simek3b662642020-07-22 17:42:43 +0200[diff] [blame]1024 xlnx,mio-bank = <1>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]1025};
1026
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]1027&uart0 {
1028 status = "okay";
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]1029 pinctrl-names = "default";
1030 pinctrl-0 = <&pinctrl_uart0_default>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]1031};
1032
1033&uart1 {
1034 status = "okay";
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]1035 pinctrl-names = "default";
1036 pinctrl-0 = <&pinctrl_uart1_default>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]1037};
1038
1039/* ULPI SMSC USB3320 */
1040&usb0 {
1041 status = "okay";
Michal Simekf7b922a2021-05-10 13:14:02 +0200[diff] [blame]1042 pinctrl-names = "default";
1043 pinctrl-0 = <&pinctrl_usb0_default>;
Manish Naranif3c63382021-07-14 06:17:19 -0600[diff] [blame]1044 phy-names = "usb3-phy";
1045 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]1046};
1047
1048&dwc3_0 {
1049 status = "okay";
1050 dr_mode = "host";
1051 snps,usb3_lpm_capable;
Michal Simekeb4b55c2021-05-31 17:51:58 +0200[diff] [blame]1052 maximum-speed = "super-speed";
Michal Simek1a79c272018-03-28 15:43:51 +0200[diff] [blame]1053};
1054
1055&watchdog0 {
1056 status = "okay";
1057};
Michal Simek6412f602021-05-27 13:44:35 +0200[diff] [blame]1058
1059&zynqmp_dpdma {
1060 status = "okay";
1061};
1062
1063&zynqmp_dpsub {
1064 status = "okay";
1065 phy-names = "dp-phy0", "dp-phy1";
1066 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
1067 <&psgtr 0 PHY_TYPE_DP 1 3>;
1068};