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git01.mediatek.com / filogic / uboot / f70dc3650f970c012b35f5476eefe779e82e33ba / . / arch / arm / dts / imx8mp-data-modul-edm-sbc-u-boot.dtsi
blob: cb6ea356fd7bfcf232779f769c0be17ec96319af [file] [log] [blame]
Marek Vasutaa2fc532023-04-04 01:07:43 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2022 Marek Vasut <marex@denx.de>
4 */
5
6#include "imx8mp-u-boot.dtsi"
Marek Vasut3869f2d2023-07-15 20:24:16 +0200[diff] [blame]7#include "imx8mp-pinfunc.h"
Marek Vasutaa2fc532023-04-04 01:07:43 +0200[diff] [blame]8
9/ {
10 aliases {
11 eeprom0 = &eeprom;
12 mmc0 = &usdhc3; /* eMMC */
13 mmc1 = &usdhc2; /* MicroSD */
14 spi0 = &ecspi1;
15 };
16
17 config {
18 dmo,ram-coding-gpios = <&gpio3 20 0>, <&gpio4 3 0>, <&gpio4 1 0>;
19 };
20
Marek Vasut3869f2d2023-07-15 20:24:16 +0200[diff] [blame]21 reg_usb1_vbus: regulator-usb1-vbus {
22 compatible = "regulator-fixed";
23 enable-active-high;
24 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_usb1_vbus>;
27 regulator-max-microvolt = <5000000>;
28 regulator-min-microvolt = <5000000>;
29 regulator-name = "USB1_PWR";
30 };
31
Marek Vasutaa2fc532023-04-04 01:07:43 +0200[diff] [blame]32 wdt-reboot {
33 compatible = "wdt-reboot";
34 wdt = <&wdog1>;
35 bootph-pre-ram;
36 };
37};
38
39&buck4 {
40 bootph-pre-ram;
41};
42
43&buck5 {
44 bootph-pre-ram;
45};
46
47&ecspi1 {
48 bootph-pre-ram;
49 flash@0 {
50 bootph-pre-ram;
51 };
52};
53
Marek Vasutaa2fc532023-04-04 01:07:43 +0200[diff] [blame]54&gpio1 {
55 bootph-pre-ram;
56};
57
58&gpio2 {
59 bootph-pre-ram;
60};
61
62&gpio3 {
63 bootph-pre-ram;
Marek Vasut602accd2023-12-18 19:02:14 +0100[diff] [blame]64
65 bl-enable-hog {
66 bootph-pre-ram;
67 gpio-hog;
68 output-low;
69 gpios = <0 GPIO_ACTIVE_HIGH>;
70 line-name = "BL_ENABLE_1V8";
71 };
72
73 tft-enable-hog {
74 bootph-pre-ram;
75 gpio-hog;
76 output-low;
77 gpios = <6 GPIO_ACTIVE_HIGH>;
78 line-name = "TFT_ENABLE_1V8";
79 };
80
81 graphics-gpio0-hog {
82 bootph-pre-ram;
83 gpio-hog;
84 input;
85 gpios = <7 GPIO_ACTIVE_HIGH>;
86 line-name = "GRAPHICS_GPIO0_1V8";
87 };
Marek Vasutaa2fc532023-04-04 01:07:43 +0200[diff] [blame]88};
89
90&gpio4 {
91 bootph-pre-ram;
Marek Vasut602accd2023-12-18 19:02:14 +0100[diff] [blame]92
93 dsi-reset-hog {
94 bootph-pre-ram;
95 gpio-hog;
96 output-high;
97 gpios = <0 GPIO_ACTIVE_LOW>;
98 line-name = "DSI_RESET_1V8#";
99 };
100
101 graphics-prsnt-hog {
102 bootph-pre-ram;
103 gpio-hog;
104 input;
105 gpios = <18 GPIO_ACTIVE_LOW>;
106 line-name = "GRAPHICS_PRSNT_1V8#";
107 };
108
109 dsi-irq-hog {
110 bootph-pre-ram;
111 gpio-hog;
112 input;
113 gpios = <19 GPIO_ACTIVE_LOW>;
114 line-name = "DSI_IRQ_1V8#";
115 };
Marek Vasutaa2fc532023-04-04 01:07:43 +0200[diff] [blame]116};
117
118&gpio5 {
119 bootph-pre-ram;
120};
121
122&i2c3 {
123 bootph-pre-ram;
124};
125
126&pinctrl_ecspi1 {
127 bootph-pre-ram;
128};
129
130&pinctrl_hog_sbc {
131 bootph-pre-ram;
132};
133
134&pinctrl_i2c3 {
135 bootph-pre-ram;
136};
137
138&pinctrl_i2c3_gpio {
139 bootph-pre-ram;
140};
141
142&pinctrl_pmic {
143 bootph-pre-ram;
144};
145
146&pinctrl_uart3 {
147 bootph-pre-ram;
148};
149
150&pinctrl_usdhc2 {
151 bootph-pre-ram;
152};
153
154&pinctrl_usdhc3 {
155 bootph-pre-ram;
156};
157
158&pmic {
159 bootph-pre-ram;
160
161 regulators {
162 bootph-pre-ram;
163 };
164};
165
166&uart3 {
167 bootph-pre-ram;
168};
169
Marek Vasut3869f2d2023-07-15 20:24:16 +0200[diff] [blame]170&usb3_phy0 {
171 vbus-supply = <&reg_usb1_vbus>;
172};
173
Marek Vasutaa2fc532023-04-04 01:07:43 +0200[diff] [blame]174&usdhc2 {
175 bootph-pre-ram;
176 sd-uhs-sdr104;
177 sd-uhs-ddr50;
178};
179
180&usdhc3 {
181 bootph-pre-ram;
182 mmc-hs400-1_8v;
183 mmc-hs400-enhanced-strobe;
184};
185
186&wdog1 {
187 bootph-pre-ram;
188};
Marek Vasut3869f2d2023-07-15 20:24:16 +0200[diff] [blame]189
190&iomuxc {
191 usb1-grp {
192 fsl,pins = <
193 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x80
194 >;
195 };
196
197 pinctrl_usb1_vbus: usb1-vbus-grp {
198 fsl,pins = <
199 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x6
200 >;
201 };
202};