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git01.mediatek.com / filogic / uboot / ef3e30bf61752ea7b730c3088cb3d3d995676f19 / . / arch / arm / dts / nuvoton-common-npcm8xx.dtsi
blob: aa7aac8c3774c836d54a4f0b0ed4d9bfdb42fbee [file] [log] [blame]
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
3
4#include <dt-bindings/clock/nuvoton,npcm845-clk.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/interrupt-controller/irq.h>
7
8/ {
9 #address-cells = <2>;
10 #size-cells = <2>;
11 interrupt-parent = <&gic>;
12
13 soc {
14 #address-cells = <2>;
15 #size-cells = <2>;
16 compatible = "simple-bus";
17 interrupt-parent = <&gic>;
18 ranges;
19
20 gcr: system-controller@f0800000 {
21 compatible = "nuvoton,npcm845-gcr", "syscon";
22 reg = <0x0 0xf0800000 0x0 0x1000>;
23 };
24
25 gic: interrupt-controller@dfff9000 {
26 compatible = "arm,gic-400";
27 reg = <0x0 0xdfff9000 0x0 0x1000>,
28 <0x0 0xdfffa000 0x0 0x2000>,
29 <0x0 0xdfffc000 0x0 0x2000>,
30 <0x0 0xdfffe000 0x0 0x2000>;
31 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
32 #interrupt-cells = <3>;
33 interrupt-controller;
34 #address-cells = <0>;
35 ppi-partitions {
36 ppi_cluster0: interrupt-partition-0 {
37 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
38 };
39 };
40 };
41 };
42
43 ahb {
44 #address-cells = <2>;
45 #size-cells = <2>;
46 compatible = "simple-bus";
47 interrupt-parent = <&gic>;
48 ranges;
49
50 rstc: reset-controller@f0801000 {
51 compatible = "nuvoton,npcm845-reset";
52 reg = <0x0 0xf0801000 0x0 0x78>;
53 #reset-cells = <2>;
54 nuvoton,sysgcr = <&gcr>;
55 };
56
57 clk: clock-controller@f0801000 {
58 compatible = "nuvoton,npcm845-clk";
59 #clock-cells = <1>;
60 reg = <0x0 0xf0801000 0x0 0x1000>;
61 };
62
63 apb {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "simple-bus";
67 interrupt-parent = <&gic>;
68 ranges = <0x0 0x0 0xf0000000 0x00300000>,
69 <0xfff00000 0x0 0xfff00000 0x00016000>;
70
71 timer0: timer@8000 {
72 compatible = "nuvoton,npcm845-timer";
73 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
74 reg = <0x8000 0x1C>;
75 clocks = <&clk NPCM8XX_CLK_REFCLK>;
76 clock-names = "refclk";
77 };
78
79 serial0: serial@0 {
80 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
81 reg = <0x0 0x1000>;
82 clocks = <&clk NPCM8XX_CLK_UART>;
83 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
84 reg-shift = <2>;
85 status = "disabled";
86 };
87
88 serial1: serial@1000 {
89 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
90 reg = <0x1000 0x1000>;
91 clocks = <&clk NPCM8XX_CLK_UART>;
92 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
93 reg-shift = <2>;
94 status = "disabled";
95 };
96
97 serial2: serial@2000 {
98 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
99 reg = <0x2000 0x1000>;
100 clocks = <&clk NPCM8XX_CLK_UART>;
101 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
102 reg-shift = <2>;
103 status = "disabled";
104 };
105
106 serial3: serial@3000 {
107 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
108 reg = <0x3000 0x1000>;
109 clocks = <&clk NPCM8XX_CLK_UART>;
110 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
111 reg-shift = <2>;
112 status = "disabled";
113 };
114
115 serial4: serial@4000 {
116 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
117 reg = <0x4000 0x1000>;
118 clocks = <&clk NPCM8XX_CLK_UART>;
119 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
120 reg-shift = <2>;
121 status = "disabled";
122 };
123
124 serial5: serial@5000 {
125 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
126 reg = <0x5000 0x1000>;
127 clocks = <&clk NPCM8XX_CLK_UART>;
128 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
129 reg-shift = <2>;
130 status = "disabled";
131 };
132
133 serial6: serial@6000 {
134 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
135 reg = <0x6000 0x1000>;
136 clocks = <&clk NPCM8XX_CLK_UART>;
137 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
138 reg-shift = <2>;
139 status = "disabled";
140 };
141
142 watchdog0: watchdog@801c {
143 compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
144 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
145 reg = <0x801c 0x4>;
146 status = "disabled";
147 clocks = <&clk NPCM8XX_CLK_REFCLK>;
148 syscon = <&gcr>;
149 };
150
151 watchdog1: watchdog@901c {
152 compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
153 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
154 reg = <0x901c 0x4>;
155 status = "disabled";
156 clocks = <&clk NPCM8XX_CLK_REFCLK>;
157 syscon = <&gcr>;
158 };
159
160 watchdog2: watchdog@a01c {
161 compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
162 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
163 reg = <0xa01c 0x4>;
164 status = "disabled";
165 clocks = <&clk NPCM8XX_CLK_REFCLK>;
166 syscon = <&gcr>;
167 };
168 };
169 };
170};