Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Freescale i.MX28 SSP Register Definitions |
| 3 | * |
| 4 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> |
| 5 | * |
| 6 | * Based on code from LTIB: |
| 7 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #ifndef __MX28_REGS_SSP_H__ |
| 26 | #define __MX28_REGS_SSP_H__ |
| 27 | |
| 28 | #include <asm/arch/regs-common.h> |
| 29 | |
| 30 | #ifndef __ASSEMBLY__ |
Marek Vasut | fb3db4e | 2013-01-22 15:01:01 +0000 | [diff] [blame] | 31 | #if defined(CONFIG_MX23) |
Otavio Salvador | 22f4ff9 | 2012-08-05 09:05:31 +0000 | [diff] [blame] | 32 | struct mxs_ssp_regs { |
Otavio Salvador | 5309b00 | 2012-08-05 09:05:30 +0000 | [diff] [blame] | 33 | mxs_reg_32(hw_ssp_ctrl0) |
| 34 | mxs_reg_32(hw_ssp_cmd0) |
| 35 | mxs_reg_32(hw_ssp_cmd1) |
Marek Vasut | fb3db4e | 2013-01-22 15:01:01 +0000 | [diff] [blame] | 36 | mxs_reg_32(hw_ssp_compref) |
| 37 | mxs_reg_32(hw_ssp_compmask) |
| 38 | mxs_reg_32(hw_ssp_timing) |
| 39 | mxs_reg_32(hw_ssp_ctrl1) |
| 40 | mxs_reg_32(hw_ssp_data) |
| 41 | mxs_reg_32(hw_ssp_sdresp0) |
| 42 | mxs_reg_32(hw_ssp_sdresp1) |
| 43 | mxs_reg_32(hw_ssp_sdresp2) |
| 44 | mxs_reg_32(hw_ssp_sdresp3) |
| 45 | mxs_reg_32(hw_ssp_status) |
| 46 | |
| 47 | uint32_t reserved1[12]; |
| 48 | |
| 49 | mxs_reg_32(hw_ssp_debug) |
| 50 | mxs_reg_32(hw_ssp_version) |
| 51 | }; |
| 52 | #elif defined(CONFIG_MX28) |
| 53 | struct mxs_ssp_regs { |
| 54 | mxs_reg_32(hw_ssp_ctrl0) |
| 55 | mxs_reg_32(hw_ssp_cmd0) |
| 56 | mxs_reg_32(hw_ssp_cmd1) |
Otavio Salvador | 5309b00 | 2012-08-05 09:05:30 +0000 | [diff] [blame] | 57 | mxs_reg_32(hw_ssp_xfer_size) |
| 58 | mxs_reg_32(hw_ssp_block_size) |
| 59 | mxs_reg_32(hw_ssp_compref) |
| 60 | mxs_reg_32(hw_ssp_compmask) |
| 61 | mxs_reg_32(hw_ssp_timing) |
| 62 | mxs_reg_32(hw_ssp_ctrl1) |
| 63 | mxs_reg_32(hw_ssp_data) |
| 64 | mxs_reg_32(hw_ssp_sdresp0) |
| 65 | mxs_reg_32(hw_ssp_sdresp1) |
| 66 | mxs_reg_32(hw_ssp_sdresp2) |
| 67 | mxs_reg_32(hw_ssp_sdresp3) |
| 68 | mxs_reg_32(hw_ssp_ddr_ctrl) |
| 69 | mxs_reg_32(hw_ssp_dll_ctrl) |
| 70 | mxs_reg_32(hw_ssp_status) |
| 71 | mxs_reg_32(hw_ssp_dll_sts) |
| 72 | mxs_reg_32(hw_ssp_debug) |
| 73 | mxs_reg_32(hw_ssp_version) |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 74 | }; |
Marek Vasut | fb3db4e | 2013-01-22 15:01:01 +0000 | [diff] [blame] | 75 | #endif |
Marek Vasut | 9602661 | 2013-01-11 03:19:02 +0000 | [diff] [blame] | 76 | |
| 77 | static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) |
| 78 | { |
| 79 | switch (port) { |
| 80 | case 0: |
| 81 | return (struct mxs_ssp_regs *)MXS_SSP0_BASE; |
| 82 | case 1: |
| 83 | return (struct mxs_ssp_regs *)MXS_SSP1_BASE; |
Marek Vasut | 17f09c7 | 2013-01-11 03:19:07 +0000 | [diff] [blame] | 84 | #ifdef CONFIG_MX28 |
Marek Vasut | 9602661 | 2013-01-11 03:19:02 +0000 | [diff] [blame] | 85 | case 2: |
| 86 | return (struct mxs_ssp_regs *)MXS_SSP2_BASE; |
| 87 | case 3: |
| 88 | return (struct mxs_ssp_regs *)MXS_SSP3_BASE; |
Marek Vasut | 17f09c7 | 2013-01-11 03:19:07 +0000 | [diff] [blame] | 89 | #endif |
Marek Vasut | 9602661 | 2013-01-11 03:19:02 +0000 | [diff] [blame] | 90 | default: |
| 91 | return NULL; |
| 92 | } |
| 93 | } |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 94 | #endif |
| 95 | |
| 96 | #define SSP_CTRL0_SFTRST (1 << 31) |
| 97 | #define SSP_CTRL0_CLKGATE (1 << 30) |
| 98 | #define SSP_CTRL0_RUN (1 << 29) |
| 99 | #define SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) |
| 100 | #define SSP_CTRL0_LOCK_CS (1 << 27) |
| 101 | #define SSP_CTRL0_IGNORE_CRC (1 << 26) |
| 102 | #define SSP_CTRL0_READ (1 << 25) |
| 103 | #define SSP_CTRL0_DATA_XFER (1 << 24) |
| 104 | #define SSP_CTRL0_BUS_WIDTH_MASK (0x3 << 22) |
| 105 | #define SSP_CTRL0_BUS_WIDTH_OFFSET 22 |
| 106 | #define SSP_CTRL0_BUS_WIDTH_ONE_BIT (0x0 << 22) |
| 107 | #define SSP_CTRL0_BUS_WIDTH_FOUR_BIT (0x1 << 22) |
| 108 | #define SSP_CTRL0_BUS_WIDTH_EIGHT_BIT (0x2 << 22) |
| 109 | #define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) |
| 110 | #define SSP_CTRL0_WAIT_FOR_CMD (1 << 20) |
| 111 | #define SSP_CTRL0_LONG_RESP (1 << 19) |
| 112 | #define SSP_CTRL0_CHECK_RESP (1 << 18) |
| 113 | #define SSP_CTRL0_GET_RESP (1 << 17) |
| 114 | #define SSP_CTRL0_ENABLE (1 << 16) |
| 115 | |
Marek Vasut | fb3db4e | 2013-01-22 15:01:01 +0000 | [diff] [blame] | 116 | #ifdef CONFIG_MX23 |
| 117 | #define SSP_CTRL0_XFER_COUNT_OFFSET 0 |
| 118 | #define SSP_CTRL0_XFER_COUNT_MASK 0xffff |
| 119 | #endif |
| 120 | |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 121 | #define SSP_CMD0_SOFT_TERMINATE (1 << 26) |
| 122 | #define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) |
| 123 | #define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24) |
| 124 | #define SSP_CMD0_BOOT_ACK_EN (1 << 23) |
| 125 | #define SSP_CMD0_SLOW_CLKING_EN (1 << 22) |
| 126 | #define SSP_CMD0_CONT_CLKING_EN (1 << 21) |
| 127 | #define SSP_CMD0_APPEND_8CYC (1 << 20) |
Marek Vasut | fb3db4e | 2013-01-22 15:01:01 +0000 | [diff] [blame] | 128 | #if defined(CONFIG_MX23) |
| 129 | #define SSP_CMD0_BLOCK_SIZE_MASK (0xf << 16) |
| 130 | #define SSP_CMD0_BLOCK_SIZE_OFFSET 16 |
| 131 | #define SSP_CMD0_BLOCK_COUNT_MASK (0xff << 8) |
| 132 | #define SSP_CMD0_BLOCK_COUNT_OFFSET 8 |
| 133 | #endif |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 134 | #define SSP_CMD0_CMD_MASK 0xff |
| 135 | #define SSP_CMD0_CMD_OFFSET 0 |
| 136 | #define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00 |
| 137 | #define SSP_CMD0_CMD_MMC_SEND_OP_COND 0x01 |
| 138 | #define SSP_CMD0_CMD_MMC_ALL_SEND_CID 0x02 |
| 139 | #define SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR 0x03 |
| 140 | #define SSP_CMD0_CMD_MMC_SET_DSR 0x04 |
| 141 | #define SSP_CMD0_CMD_MMC_RESERVED_5 0x05 |
| 142 | #define SSP_CMD0_CMD_MMC_SWITCH 0x06 |
| 143 | #define SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD 0x07 |
| 144 | #define SSP_CMD0_CMD_MMC_SEND_EXT_CSD 0x08 |
| 145 | #define SSP_CMD0_CMD_MMC_SEND_CSD 0x09 |
| 146 | #define SSP_CMD0_CMD_MMC_SEND_CID 0x0a |
| 147 | #define SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP 0x0b |
| 148 | #define SSP_CMD0_CMD_MMC_STOP_TRANSMISSION 0x0c |
| 149 | #define SSP_CMD0_CMD_MMC_SEND_STATUS 0x0d |
| 150 | #define SSP_CMD0_CMD_MMC_BUSTEST_R 0x0e |
| 151 | #define SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE 0x0f |
| 152 | #define SSP_CMD0_CMD_MMC_SET_BLOCKLEN 0x10 |
| 153 | #define SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK 0x11 |
| 154 | #define SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK 0x12 |
| 155 | #define SSP_CMD0_CMD_MMC_BUSTEST_W 0x13 |
| 156 | #define SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP 0x14 |
| 157 | #define SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT 0x17 |
| 158 | #define SSP_CMD0_CMD_MMC_WRITE_BLOCK 0x18 |
| 159 | #define SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK 0x19 |
| 160 | #define SSP_CMD0_CMD_MMC_PROGRAM_CID 0x1a |
| 161 | #define SSP_CMD0_CMD_MMC_PROGRAM_CSD 0x1b |
| 162 | #define SSP_CMD0_CMD_MMC_SET_WRITE_PROT 0x1c |
| 163 | #define SSP_CMD0_CMD_MMC_CLR_WRITE_PROT 0x1d |
| 164 | #define SSP_CMD0_CMD_MMC_SEND_WRITE_PROT 0x1e |
| 165 | #define SSP_CMD0_CMD_MMC_ERASE_GROUP_START 0x23 |
| 166 | #define SSP_CMD0_CMD_MMC_ERASE_GROUP_END 0x24 |
| 167 | #define SSP_CMD0_CMD_MMC_ERASE 0x26 |
| 168 | #define SSP_CMD0_CMD_MMC_FAST_IO 0x27 |
| 169 | #define SSP_CMD0_CMD_MMC_GO_IRQ_STATE 0x28 |
| 170 | #define SSP_CMD0_CMD_MMC_LOCK_UNLOCK 0x2a |
| 171 | #define SSP_CMD0_CMD_MMC_APP_CMD 0x37 |
| 172 | #define SSP_CMD0_CMD_MMC_GEN_CMD 0x38 |
| 173 | #define SSP_CMD0_CMD_SD_GO_IDLE_STATE 0x00 |
| 174 | #define SSP_CMD0_CMD_SD_ALL_SEND_CID 0x02 |
| 175 | #define SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR 0x03 |
| 176 | #define SSP_CMD0_CMD_SD_SET_DSR 0x04 |
| 177 | #define SSP_CMD0_CMD_SD_IO_SEND_OP_COND 0x05 |
| 178 | #define SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD 0x07 |
| 179 | #define SSP_CMD0_CMD_SD_SEND_CSD 0x09 |
| 180 | #define SSP_CMD0_CMD_SD_SEND_CID 0x0a |
| 181 | #define SSP_CMD0_CMD_SD_STOP_TRANSMISSION 0x0c |
| 182 | #define SSP_CMD0_CMD_SD_SEND_STATUS 0x0d |
| 183 | #define SSP_CMD0_CMD_SD_GO_INACTIVE_STATE 0x0f |
| 184 | #define SSP_CMD0_CMD_SD_SET_BLOCKLEN 0x10 |
| 185 | #define SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK 0x11 |
| 186 | #define SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK 0x12 |
| 187 | #define SSP_CMD0_CMD_SD_WRITE_BLOCK 0x18 |
| 188 | #define SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK 0x19 |
| 189 | #define SSP_CMD0_CMD_SD_PROGRAM_CSD 0x1b |
| 190 | #define SSP_CMD0_CMD_SD_SET_WRITE_PROT 0x1c |
| 191 | #define SSP_CMD0_CMD_SD_CLR_WRITE_PROT 0x1d |
| 192 | #define SSP_CMD0_CMD_SD_SEND_WRITE_PROT 0x1e |
| 193 | #define SSP_CMD0_CMD_SD_ERASE_WR_BLK_START 0x20 |
| 194 | #define SSP_CMD0_CMD_SD_ERASE_WR_BLK_END 0x21 |
| 195 | #define SSP_CMD0_CMD_SD_ERASE_GROUP_START 0x23 |
| 196 | #define SSP_CMD0_CMD_SD_ERASE_GROUP_END 0x24 |
| 197 | #define SSP_CMD0_CMD_SD_ERASE 0x26 |
| 198 | #define SSP_CMD0_CMD_SD_LOCK_UNLOCK 0x2a |
| 199 | #define SSP_CMD0_CMD_SD_IO_RW_DIRECT 0x34 |
| 200 | #define SSP_CMD0_CMD_SD_IO_RW_EXTENDED 0x35 |
| 201 | #define SSP_CMD0_CMD_SD_APP_CMD 0x37 |
| 202 | #define SSP_CMD0_CMD_SD_GEN_CMD 0x38 |
| 203 | |
| 204 | #define SSP_CMD1_CMD_ARG_MASK 0xffffffff |
| 205 | #define SSP_CMD1_CMD_ARG_OFFSET 0 |
| 206 | |
Marek Vasut | fb3db4e | 2013-01-22 15:01:01 +0000 | [diff] [blame] | 207 | #if defined(CONFIG_MX28) |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 208 | #define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff |
| 209 | #define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0 |
| 210 | |
| 211 | #define SSP_BLOCK_SIZE_BLOCK_COUNT_MASK (0xffffff << 4) |
| 212 | #define SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET 4 |
| 213 | #define SSP_BLOCK_SIZE_BLOCK_SIZE_MASK 0xf |
| 214 | #define SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET 0 |
Marek Vasut | fb3db4e | 2013-01-22 15:01:01 +0000 | [diff] [blame] | 215 | #endif |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 216 | |
| 217 | #define SSP_COMPREF_REFERENCE_MASK 0xffffffff |
| 218 | #define SSP_COMPREF_REFERENCE_OFFSET 0 |
| 219 | |
| 220 | #define SSP_COMPMASK_MASK_MASK 0xffffffff |
| 221 | #define SSP_COMPMASK_MASK_OFFSET 0 |
| 222 | |
| 223 | #define SSP_TIMING_TIMEOUT_MASK (0xffff << 16) |
| 224 | #define SSP_TIMING_TIMEOUT_OFFSET 16 |
| 225 | #define SSP_TIMING_CLOCK_DIVIDE_MASK (0xff << 8) |
| 226 | #define SSP_TIMING_CLOCK_DIVIDE_OFFSET 8 |
| 227 | #define SSP_TIMING_CLOCK_RATE_MASK 0xff |
| 228 | #define SSP_TIMING_CLOCK_RATE_OFFSET 0 |
| 229 | |
| 230 | #define SSP_CTRL1_SDIO_IRQ (1 << 31) |
| 231 | #define SSP_CTRL1_SDIO_IRQ_EN (1 << 30) |
| 232 | #define SSP_CTRL1_RESP_ERR_IRQ (1 << 29) |
| 233 | #define SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) |
| 234 | #define SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) |
| 235 | #define SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) |
| 236 | #define SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) |
| 237 | #define SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) |
| 238 | #define SSP_CTRL1_DATA_CRC_IRQ (1 << 23) |
| 239 | #define SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) |
| 240 | #define SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) |
| 241 | #define SSP_CTRL1_FIFO_UNDERRUN_EN (1 << 20) |
| 242 | #define SSP_CTRL1_CEATA_CCS_ERR_IRQ (1 << 19) |
| 243 | #define SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN (1 << 18) |
| 244 | #define SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) |
| 245 | #define SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) |
| 246 | #define SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) |
| 247 | #define SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) |
| 248 | #define SSP_CTRL1_DMA_ENABLE (1 << 13) |
| 249 | #define SSP_CTRL1_CEATA_CCS_ERR_EN (1 << 12) |
| 250 | #define SSP_CTRL1_SLAVE_OUT_DISABLE (1 << 11) |
| 251 | #define SSP_CTRL1_PHASE (1 << 10) |
| 252 | #define SSP_CTRL1_POLARITY (1 << 9) |
| 253 | #define SSP_CTRL1_SLAVE_MODE (1 << 8) |
| 254 | #define SSP_CTRL1_WORD_LENGTH_MASK (0xf << 4) |
| 255 | #define SSP_CTRL1_WORD_LENGTH_OFFSET 4 |
| 256 | #define SSP_CTRL1_WORD_LENGTH_RESERVED0 (0x0 << 4) |
| 257 | #define SSP_CTRL1_WORD_LENGTH_RESERVED1 (0x1 << 4) |
| 258 | #define SSP_CTRL1_WORD_LENGTH_RESERVED2 (0x2 << 4) |
| 259 | #define SSP_CTRL1_WORD_LENGTH_FOUR_BITS (0x3 << 4) |
| 260 | #define SSP_CTRL1_WORD_LENGTH_EIGHT_BITS (0x7 << 4) |
| 261 | #define SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS (0xf << 4) |
| 262 | #define SSP_CTRL1_SSP_MODE_MASK 0xf |
| 263 | #define SSP_CTRL1_SSP_MODE_OFFSET 0 |
| 264 | #define SSP_CTRL1_SSP_MODE_SPI 0x0 |
| 265 | #define SSP_CTRL1_SSP_MODE_SSI 0x1 |
| 266 | #define SSP_CTRL1_SSP_MODE_SD_MMC 0x3 |
| 267 | #define SSP_CTRL1_SSP_MODE_MS 0x4 |
| 268 | |
| 269 | #define SSP_DATA_DATA_MASK 0xffffffff |
| 270 | #define SSP_DATA_DATA_OFFSET 0 |
| 271 | |
| 272 | #define SSP_SDRESP0_RESP0_MASK 0xffffffff |
| 273 | #define SSP_SDRESP0_RESP0_OFFSET 0 |
| 274 | |
| 275 | #define SSP_SDRESP1_RESP1_MASK 0xffffffff |
| 276 | #define SSP_SDRESP1_RESP1_OFFSET 0 |
| 277 | |
| 278 | #define SSP_SDRESP2_RESP2_MASK 0xffffffff |
| 279 | #define SSP_SDRESP2_RESP2_OFFSET 0 |
| 280 | |
| 281 | #define SSP_SDRESP3_RESP3_MASK 0xffffffff |
| 282 | #define SSP_SDRESP3_RESP3_OFFSET 0 |
| 283 | |
| 284 | #define SSP_DDR_CTRL_DMA_BURST_TYPE_MASK (0x3 << 30) |
| 285 | #define SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET 30 |
| 286 | #define SSP_DDR_CTRL_NIBBLE_POS (1 << 1) |
| 287 | #define SSP_DDR_CTRL_TXCLK_DELAY_TYPE (1 << 0) |
| 288 | |
| 289 | #define SSP_DLL_CTRL_REF_UPDATE_INT_MASK (0xf << 28) |
| 290 | #define SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET 28 |
| 291 | #define SSP_DLL_CTRL_SLV_UPDATE_INT_MASK (0xff << 20) |
| 292 | #define SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET 20 |
| 293 | #define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3f << 10) |
| 294 | #define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET 10 |
| 295 | #define SSP_DLL_CTRL_SLV_OVERRIDE (1 << 9) |
| 296 | #define SSP_DLL_CTRL_GATE_UPDATE (1 << 7) |
| 297 | #define SSP_DLL_CTRL_SLV_DLY_TARGET_MASK (0xf << 3) |
| 298 | #define SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET 3 |
| 299 | #define SSP_DLL_CTRL_SLV_FORCE_UPD (1 << 2) |
| 300 | #define SSP_DLL_CTRL_RESET (1 << 1) |
| 301 | #define SSP_DLL_CTRL_ENABLE (1 << 0) |
| 302 | |
| 303 | #define SSP_STATUS_PRESENT (1 << 31) |
| 304 | #define SSP_STATUS_MS_PRESENT (1 << 30) |
| 305 | #define SSP_STATUS_SD_PRESENT (1 << 29) |
| 306 | #define SSP_STATUS_CARD_DETECT (1 << 28) |
| 307 | #define SSP_STATUS_DMABURST (1 << 22) |
| 308 | #define SSP_STATUS_DMASENSE (1 << 21) |
| 309 | #define SSP_STATUS_DMATERM (1 << 20) |
| 310 | #define SSP_STATUS_DMAREQ (1 << 19) |
| 311 | #define SSP_STATUS_DMAEND (1 << 18) |
| 312 | #define SSP_STATUS_SDIO_IRQ (1 << 17) |
| 313 | #define SSP_STATUS_RESP_CRC_ERR (1 << 16) |
| 314 | #define SSP_STATUS_RESP_ERR (1 << 15) |
| 315 | #define SSP_STATUS_RESP_TIMEOUT (1 << 14) |
| 316 | #define SSP_STATUS_DATA_CRC_ERR (1 << 13) |
| 317 | #define SSP_STATUS_TIMEOUT (1 << 12) |
| 318 | #define SSP_STATUS_RECV_TIMEOUT_STAT (1 << 11) |
| 319 | #define SSP_STATUS_CEATA_CCS_ERR (1 << 10) |
| 320 | #define SSP_STATUS_FIFO_OVRFLW (1 << 9) |
| 321 | #define SSP_STATUS_FIFO_FULL (1 << 8) |
| 322 | #define SSP_STATUS_FIFO_EMPTY (1 << 5) |
| 323 | #define SSP_STATUS_FIFO_UNDRFLW (1 << 4) |
| 324 | #define SSP_STATUS_CMD_BUSY (1 << 3) |
| 325 | #define SSP_STATUS_DATA_BUSY (1 << 2) |
| 326 | #define SSP_STATUS_BUSY (1 << 0) |
| 327 | |
| 328 | #define SSP_DLL_STS_REF_SEL_MASK (0x3f << 8) |
| 329 | #define SSP_DLL_STS_REF_SEL_OFFSET 8 |
| 330 | #define SSP_DLL_STS_SLV_SEL_MASK (0x3f << 2) |
| 331 | #define SSP_DLL_STS_SLV_SEL_OFFSET 2 |
| 332 | #define SSP_DLL_STS_REF_LOCK (1 << 1) |
| 333 | #define SSP_DLL_STS_SLV_LOCK (1 << 0) |
| 334 | |
| 335 | #define SSP_DEBUG_DATACRC_ERR_MASK (0xf << 28) |
| 336 | #define SSP_DEBUG_DATACRC_ERR_OFFSET 28 |
| 337 | #define SSP_DEBUG_DATA_STALL (1 << 27) |
| 338 | #define SSP_DEBUG_DAT_SM_MASK (0x7 << 24) |
| 339 | #define SSP_DEBUG_DAT_SM_OFFSET 24 |
| 340 | #define SSP_DEBUG_DAT_SM_DSM_IDLE (0x0 << 24) |
| 341 | #define SSP_DEBUG_DAT_SM_DSM_WORD (0x2 << 24) |
| 342 | #define SSP_DEBUG_DAT_SM_DSM_CRC1 (0x3 << 24) |
| 343 | #define SSP_DEBUG_DAT_SM_DSM_CRC2 (0x4 << 24) |
| 344 | #define SSP_DEBUG_DAT_SM_DSM_END (0x5 << 24) |
| 345 | #define SSP_DEBUG_MSTK_SM_MASK (0xf << 20) |
| 346 | #define SSP_DEBUG_MSTK_SM_OFFSET 20 |
| 347 | #define SSP_DEBUG_MSTK_SM_MSTK_IDLE (0x0 << 20) |
| 348 | #define SSP_DEBUG_MSTK_SM_MSTK_CKON (0x1 << 20) |
| 349 | #define SSP_DEBUG_MSTK_SM_MSTK_BS1 (0x2 << 20) |
| 350 | #define SSP_DEBUG_MSTK_SM_MSTK_TPC (0x3 << 20) |
| 351 | #define SSP_DEBUG_MSTK_SM_MSTK_BS2 (0x4 << 20) |
| 352 | #define SSP_DEBUG_MSTK_SM_MSTK_HDSHK (0x5 << 20) |
| 353 | #define SSP_DEBUG_MSTK_SM_MSTK_BS3 (0x6 << 20) |
| 354 | #define SSP_DEBUG_MSTK_SM_MSTK_RW (0x7 << 20) |
| 355 | #define SSP_DEBUG_MSTK_SM_MSTK_CRC1 (0x8 << 20) |
| 356 | #define SSP_DEBUG_MSTK_SM_MSTK_CRC2 (0x9 << 20) |
| 357 | #define SSP_DEBUG_MSTK_SM_MSTK_BS0 (0xa << 20) |
| 358 | #define SSP_DEBUG_MSTK_SM_MSTK_END1 (0xb << 20) |
| 359 | #define SSP_DEBUG_MSTK_SM_MSTK_END2W (0xc << 20) |
| 360 | #define SSP_DEBUG_MSTK_SM_MSTK_END2R (0xd << 20) |
| 361 | #define SSP_DEBUG_MSTK_SM_MSTK_DONE (0xe << 20) |
| 362 | #define SSP_DEBUG_CMD_OE (1 << 19) |
| 363 | #define SSP_DEBUG_DMA_SM_MASK (0x7 << 16) |
| 364 | #define SSP_DEBUG_DMA_SM_OFFSET 16 |
| 365 | #define SSP_DEBUG_DMA_SM_DMA_IDLE (0x0 << 16) |
| 366 | #define SSP_DEBUG_DMA_SM_DMA_DMAREQ (0x1 << 16) |
| 367 | #define SSP_DEBUG_DMA_SM_DMA_DMAACK (0x2 << 16) |
| 368 | #define SSP_DEBUG_DMA_SM_DMA_STALL (0x3 << 16) |
| 369 | #define SSP_DEBUG_DMA_SM_DMA_BUSY (0x4 << 16) |
| 370 | #define SSP_DEBUG_DMA_SM_DMA_DONE (0x5 << 16) |
| 371 | #define SSP_DEBUG_DMA_SM_DMA_COUNT (0x6 << 16) |
| 372 | #define SSP_DEBUG_MMC_SM_MASK (0xf << 12) |
| 373 | #define SSP_DEBUG_MMC_SM_OFFSET 12 |
| 374 | #define SSP_DEBUG_MMC_SM_MMC_IDLE (0x0 << 12) |
| 375 | #define SSP_DEBUG_MMC_SM_MMC_CMD (0x1 << 12) |
| 376 | #define SSP_DEBUG_MMC_SM_MMC_TRC (0x2 << 12) |
| 377 | #define SSP_DEBUG_MMC_SM_MMC_RESP (0x3 << 12) |
| 378 | #define SSP_DEBUG_MMC_SM_MMC_RPRX (0x4 << 12) |
| 379 | #define SSP_DEBUG_MMC_SM_MMC_TX (0x5 << 12) |
| 380 | #define SSP_DEBUG_MMC_SM_MMC_CTOK (0x6 << 12) |
| 381 | #define SSP_DEBUG_MMC_SM_MMC_RX (0x7 << 12) |
| 382 | #define SSP_DEBUG_MMC_SM_MMC_CCS (0x8 << 12) |
| 383 | #define SSP_DEBUG_MMC_SM_MMC_PUP (0x9 << 12) |
| 384 | #define SSP_DEBUG_MMC_SM_MMC_WAIT (0xa << 12) |
| 385 | #define SSP_DEBUG_CMD_SM_MASK (0x3 << 10) |
| 386 | #define SSP_DEBUG_CMD_SM_OFFSET 10 |
| 387 | #define SSP_DEBUG_CMD_SM_CSM_IDLE (0x0 << 10) |
| 388 | #define SSP_DEBUG_CMD_SM_CSM_INDEX (0x1 << 10) |
| 389 | #define SSP_DEBUG_CMD_SM_CSM_ARG (0x2 << 10) |
| 390 | #define SSP_DEBUG_CMD_SM_CSM_CRC (0x3 << 10) |
| 391 | #define SSP_DEBUG_SSP_CMD (1 << 9) |
| 392 | #define SSP_DEBUG_SSP_RESP (1 << 8) |
| 393 | #define SSP_DEBUG_SSP_RXD_MASK 0xff |
| 394 | #define SSP_DEBUG_SSP_RXD_OFFSET 0 |
| 395 | |
| 396 | #define SSP_VERSION_MAJOR_MASK (0xff << 24) |
| 397 | #define SSP_VERSION_MAJOR_OFFSET 24 |
| 398 | #define SSP_VERSION_MINOR_MASK (0xff << 16) |
| 399 | #define SSP_VERSION_MINOR_OFFSET 16 |
| 400 | #define SSP_VERSION_STEP_MASK 0xffff |
| 401 | #define SSP_VERSION_STEP_OFFSET 0 |
| 402 | |
| 403 | #endif /* __MX28_REGS_SSP_H__ */ |