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git01.mediatek.com / filogic / uboot / ed2724bba86823df712326f3ade7bbe41d7601c7 / . / arch / arm / dts / imx8mq-kontron-pitx-imx8m.dts
blob: a91c136797f60d6766fb223bbb2f7cd8374ce417 [file] [log] [blame]
Heiko Thiery05a3d952022-01-31 17:30:45 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree File for the Kontron pitx-imx8m board.
4 *
5 * Copyright (C) 2021 Heiko Thiery <heiko.thiery@gmail.com>
6 */
7
8/dts-v1/;
9
10#include "imx8mq.dtsi"
11#include <dt-bindings/net/ti-dp83867.h>
12
13/ {
14 model = "Kontron pITX-imx8m";
15 compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
16
17 aliases {
18 i2c0 = &i2c1;
19 i2c1 = &i2c2;
20 i2c2 = &i2c3;
21 mmc0 = &usdhc1;
22 mmc1 = &usdhc2;
23 serial0 = &uart1;
24 serial1 = &uart2;
25 serial2 = &uart3;
26 spi0 = &qspi0;
27 spi1 = &ecspi2;
28 };
29
30 chosen {
31 stdout-path = "serial2:115200n8";
32 };
33
34 pcie0_refclk: pcie0-clock {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <100000000>;
38 };
39
40 pcie1_refclk: pcie1-clock {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <100000000>;
44 };
45
46 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
47 compatible = "regulator-fixed";
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_reg_usdhc2>;
50 regulator-name = "V_3V3_SD";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
Marcel Ziswiler507720a2022-07-21 15:47:59 +0200[diff] [blame]54 off-on-delay-us = <20000>;
Heiko Thiery05a3d952022-01-31 17:30:45 +0100[diff] [blame]55 enable-active-high;
56 };
57};
58
59&ecspi2 {
60 #address-cells = <1>;
61 #size-cells = <0>;
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
64 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
65 status = "okay";
66
67 tpm@0 {
68 compatible = "infineon,slb9670";
69 reg = <0>;
70 spi-max-frequency = <43000000>;
71 };
72};
73
74&fec1 {
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_fec1>;
77 phy-mode = "rgmii-id";
78 phy-handle = <&ethphy0>;
79 fsl,magic-packet;
80 status = "okay";
81
82 mdio {
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 ethphy0: ethernet-phy@0 {
87 compatible = "ethernet-phy-ieee802.3-c22";
88 reg = <0>;
89 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
90 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
91 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
92 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
93 reset-assert-us = <10>;
94 reset-deassert-us = <280>;
95 };
96 };
97};
98
99&i2c1 {
100 clock-frequency = <400000>;
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_i2c1>;
103 status = "okay";
104
105 pmic@8 {
106 compatible = "fsl,pfuze100";
107 fsl,pfuze-support-disable-sw;
108 reg = <0x8>;
109
110 regulators {
111 sw1a_reg: sw1ab {
112 regulator-name = "V_0V9_GPU";
113 regulator-min-microvolt = <825000>;
114 regulator-max-microvolt = <1100000>;
115 };
116
117 sw1c_reg: sw1c {
118 regulator-name = "V_0V9_VPU";
119 regulator-min-microvolt = <825000>;
120 regulator-max-microvolt = <1100000>;
121 };
122
123 sw2_reg: sw2 {
124 regulator-name = "V_1V1_NVCC_DRAM";
125 regulator-min-microvolt = <1100000>;
126 regulator-max-microvolt = <1100000>;
127 regulator-always-on;
128 };
129
130 sw3a_reg: sw3ab {
131 regulator-name = "V_1V0_DRAM";
132 regulator-min-microvolt = <825000>;
133 regulator-max-microvolt = <1100000>;
134 regulator-always-on;
135 };
136
137 sw4_reg: sw4 {
138 regulator-name = "V_1V8_S0";
139 regulator-min-microvolt = <1800000>;
140 regulator-max-microvolt = <1800000>;
141 regulator-always-on;
142 };
143
144 swbst_reg: swbst {
145 regulator-name = "NC";
146 regulator-min-microvolt = <5000000>;
147 regulator-max-microvolt = <5150000>;
148 };
149
150 snvs_reg: vsnvs {
151 regulator-name = "V_0V9_SNVS";
152 regulator-min-microvolt = <1000000>;
153 regulator-max-microvolt = <3000000>;
154 regulator-always-on;
155 };
156
157 vref_reg: vrefddr {
158 regulator-name = "V_0V55_VREF_DDR";
159 regulator-always-on;
160 };
161
162 vgen1_reg: vgen1 {
163 regulator-name = "V_1V5_CSI";
164 regulator-min-microvolt = <800000>;
165 regulator-max-microvolt = <1550000>;
166 };
167
168 vgen2_reg: vgen2 {
169 regulator-name = "V_0V9_PHY";
170 regulator-min-microvolt = <850000>;
171 regulator-max-microvolt = <975000>;
172 regulator-always-on;
173 };
174
175 vgen3_reg: vgen3 {
176 regulator-name = "V_1V8_PHY";
177 regulator-min-microvolt = <1675000>;
178 regulator-max-microvolt = <1975000>;
179 regulator-always-on;
180 };
181
182 vgen4_reg: vgen4 {
183 regulator-name = "V_1V8_VDDA";
184 regulator-min-microvolt = <1625000>;
185 regulator-max-microvolt = <1875000>;
186 regulator-always-on;
187 };
188
189 vgen5_reg: vgen5 {
190 regulator-name = "V_3V3_PHY";
191 regulator-min-microvolt = <3075000>;
192 regulator-max-microvolt = <3625000>;
193 regulator-always-on;
194 };
195
196 vgen6_reg: vgen6 {
197 regulator-name = "V_2V8_CAM";
198 regulator-min-microvolt = <1800000>;
199 regulator-max-microvolt = <3300000>;
200 regulator-always-on;
201 };
202 };
203 };
204
205 fan-controller@1b {
206 compatible = "maxim,max6650";
207 reg = <0x1b>;
208 maxim,fan-microvolt = <5000000>;
209 };
210
211 rtc@32 {
212 compatible = "microcrystal,rv8803";
213 reg = <0x32>;
214 };
215
216 sensor@4b {
217 compatible = "national,lm75b";
218 reg = <0x4b>;
219 };
220
221 eeprom@51 {
222 compatible = "atmel,24c32";
223 reg = <0x51>;
224 pagesize = <32>;
225 };
226};
227
228&i2c2 {
229 clock-frequency = <100000>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_i2c2>;
232 status = "okay";
233};
234
235&i2c3 {
236 clock-frequency = <100000>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&pinctrl_i2c3>;
239 status = "okay";
240};
241
242/* M.2 B-key slot */
243&pcie0 {
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_pcie0>;
246 reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
247 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
248 <&clk IMX8MQ_CLK_PCIE1_AUX>,
249 <&clk IMX8MQ_CLK_PCIE1_PHY>,
250 <&pcie0_refclk>;
251 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
252 status = "okay";
253};
254
255/* Intel Ethernet Controller I210/I211 */
256&pcie1 {
257 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
258 <&clk IMX8MQ_CLK_PCIE2_AUX>,
259 <&clk IMX8MQ_CLK_PCIE2_PHY>,
260 <&pcie1_refclk>;
261 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
262 fsl,max-link-speed = <1>;
263 status = "okay";
264};
265
266&pgc_gpu {
267 power-supply = <&sw1a_reg>;
268};
269
270&pgc_vpu {
271 power-supply = <&sw1c_reg>;
272};
273
274&qspi0 {
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_qspi>;
277 status = "okay";
278
279 flash@0 {
280 compatible = "jedec,spi-nor";
281 #address-cells = <1>;
282 #size-cells = <1>;
283 reg = <0>;
284 spi-tx-bus-width = <1>;
285 spi-rx-bus-width = <4>;
286 m25p,fast-read;
287 spi-max-frequency = <50000000>;
288 };
289};
290
291&snvs_pwrkey {
292 status = "okay";
293};
294
295&uart1 {
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_uart1>;
298 assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
299 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
300 status = "okay";
301};
302
303&uart2 {
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_uart2>;
306 assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
307 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
308 status = "okay";
309};
310
311&uart3 {
312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_uart3>;
Marcel Ziswiler507720a2022-07-21 15:47:59 +0200[diff] [blame]314 uart-has-rtscts;
Heiko Thiery05a3d952022-01-31 17:30:45 +0100[diff] [blame]315 assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
316 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
317 status = "okay";
318};
319
320&usb3_phy0 {
321 status = "okay";
322};
323
324&usb3_phy1 {
325 status = "okay";
326};
327
328&usb_dwc3_0 {
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_usb0>;
331 dr_mode = "otg";
332 hnp-disable;
333 srp-disable;
334 adp-disable;
335 maximum-speed = "high-speed";
336 status = "okay";
337};
338
339&usb_dwc3_1 {
340 dr_mode = "host";
341 status = "okay";
342};
343
344&usdhc1 {
345 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
346 assigned-clock-rates = <400000000>;
347 pinctrl-names = "default", "state_100mhz", "state_200mhz";
348 pinctrl-0 = <&pinctrl_usdhc1>;
349 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
350 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
351 vqmmc-supply = <&sw4_reg>;
352 bus-width = <8>;
353 non-removable;
354 no-sd;
355 no-sdio;
356 status = "okay";
357};
358
359&usdhc2 {
360 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
361 assigned-clock-rates = <200000000>;
362 pinctrl-names = "default", "state_100mhz", "state_200mhz";
363 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
364 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
365 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
366 bus-width = <4>;
367 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
368 wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
369 vmmc-supply = <&reg_usdhc2_vmmc>;
370 status = "okay";
371};
372
373&wdog1 {
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_wdog>;
376 fsl,ext-reset-output;
377 status = "okay";
378};
379
380&iomuxc {
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_hog>;
383
384 pinctrl_hog: hoggrp {
385 fsl,pins = <
386 MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* TPM Reset */
387 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* USB2 Hub Reset */
388 >;
389 };
390
391 pinctrl_gpio: gpiogrp {
392 fsl,pins = <
393 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* GPIO0 */
394 MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /* GPIO1 */
395 MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* GPIO2 */
396 MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* GPIO3 */
397 MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* GPIO4 */
398 MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* GPIO5 */
399 MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* GPIO6 */
400 MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x19 /* GPIO7 */
401 >;
402 };
403
404 pinctrl_pcie0: pcie0grp {
405 fsl,pins = <
406 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x16 /* PCIE_PERST */
407 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 /* W_DISABLE */
408 >;
409 };
410
411 pinctrl_reg_usdhc2: regusdhc2gpiogrp {
412 fsl,pins = <
413 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
414 >;
415 };
416
417 pinctrl_fec1: fec1grp {
418 fsl,pins = <
419 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
420 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
421 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
422 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
423 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
424 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
425 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
426 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
427 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
428 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
429 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
430 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
431 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
432 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
433 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
434 MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
435 >;
436 };
437
438 pinctrl_i2c1: i2c1grp {
439 fsl,pins = <
440 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
441 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
442 >;
443 };
444
445 pinctrl_i2c2: i2c2grp {
446 fsl,pins = <
447 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
448 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
449 >;
450 };
451
452 pinctrl_i2c3: i2c3grp {
453 fsl,pins = <
454 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
455 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
456 >;
457 };
458
459 pinctrl_qspi: qspigrp {
460 fsl,pins = <
461 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
462 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
463 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
464 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
465 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
466 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
467 >;
468 };
469
470 pinctrl_ecspi2: ecspi2grp {
471 fsl,pins = <
472 MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19
473 MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19
474 MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19
475 >;
476 };
477
478 pinctrl_ecspi2_cs: ecspi2csgrp {
479 fsl,pins = <
480 MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
481 >;
482 };
483
484 pinctrl_uart1: uart1grp {
485 fsl,pins = <
486 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
487 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
488 >;
489 };
490
491 pinctrl_uart2: uart2grp {
492 fsl,pins = <
493 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
494 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
495 >;
496 };
497
498 pinctrl_uart3: uart3grp {
499 fsl,pins = <
500 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
501 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
502 MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
503 MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49
504 >;
505 };
506
507 pinctrl_usdhc1: usdhc1grp {
508 fsl,pins = <
509 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
510 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
511 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
512 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
513 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
514 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
515 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
516 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
517 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
518 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
519 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
520 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
521 >;
522 };
523
524 pinctrl_usdhc1_100mhz: usdhc1-100grp {
525 fsl,pins = <
526 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
527 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
528 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
529 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
530 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
531 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
532 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
533 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
534 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
535 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
536 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
537 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
538 >;
539 };
540
541 pinctrl_usdhc1_200mhz: usdhc1-200grp {
542 fsl,pins = <
543 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
544 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
545 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
546 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
547 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
548 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
549 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
550 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
551 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
552 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
553 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
554 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
555 >;
556 };
557
558 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
559 fsl,pins = <
560 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
561 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x19
562 >;
563 };
564
565 pinctrl_usdhc2: usdhc2grp {
566 fsl,pins = <
567 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
568 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
569 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
570 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
571 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
572 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
573 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
574 >;
575 };
576
577 pinctrl_usdhc2_100mhz: usdhc2-100grp {
578 fsl,pins = <
579 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
580 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
581 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
582 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
583 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
584 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
585 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
586 >;
587 };
588
589 pinctrl_usdhc2_200mhz: usdhc2-200grp {
590 fsl,pins = <
591 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
592 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
593 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
594 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
595 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
596 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
597 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
598 >;
599 };
600
601 pinctrl_usb0: usb0grp {
602 fsl,pins = <
603 MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x19
604 MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19
605 >;
606 };
607
608 pinctrl_wdog: wdoggrp {
609 fsl,pins = <
610 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
611 >;
612 };
613};