| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Jorge Ramirez-Ortiz | 9f2d1b2 | 2018-01-10 11:33:50 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Qualcomm APQ8096 sysmap |
| 4 | * |
| 5 | * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> |
| Jorge Ramirez-Ortiz | 9f2d1b2 | 2018-01-10 11:33:50 +0100 | [diff] [blame] | 6 | */ |
| 7 | #ifndef _MACH_SYSMAP_APQ8096_H |
| 8 | #define _MACH_SYSMAP_APQ8096_H |
| 9 | |
| 10 | #define TLMM_BASE_ADDR (0x1010000) |
| 11 | |
| 12 | /* Strength (sdc1) */ |
| 13 | #define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000) |
| 14 | |
| 15 | /* Clocks: (from CLK_CTL_BASE) */ |
| 16 | #define GPLL0_STATUS (0x0000) |
| 17 | #define APCS_GPLL_ENA_VOTE (0x52000) |
| Ramon Fried | ed09eef | 2019-01-12 11:47:24 +0200 | [diff] [blame^] | 18 | #define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004) |
| Jorge Ramirez-Ortiz | 9f2d1b2 | 2018-01-10 11:33:50 +0100 | [diff] [blame] | 19 | |
| 20 | #define SDCC2_BCR (0x14000) /* block reset */ |
| 21 | #define SDCC2_APPS_CBCR (0x14004) /* branch control */ |
| 22 | #define SDCC2_AHB_CBCR (0x14008) |
| 23 | #define SDCC2_CMD_RCGR (0x14010) |
| 24 | #define SDCC2_CFG_RCGR (0x14014) |
| 25 | #define SDCC2_M (0x14018) |
| 26 | #define SDCC2_N (0x1401C) |
| 27 | #define SDCC2_D (0x14020) |
| 28 | |
| Ramon Fried | ed09eef | 2019-01-12 11:47:24 +0200 | [diff] [blame^] | 29 | #define BLSP2_AHB_CBCR (0x25004) |
| 30 | #define BLSP2_UART2_APPS_CBCR (0x29004) |
| 31 | #define BLSP2_UART2_APPS_CMD_RCGR (0x2900C) |
| 32 | #define BLSP2_UART2_APPS_CFG_RCGR (0x29010) |
| 33 | #define BLSP2_UART2_APPS_M (0x29014) |
| 34 | #define BLSP2_UART2_APPS_N (0x29018) |
| 35 | #define BLSP2_UART2_APPS_D (0x2901C) |
| 36 | |
| Jorge Ramirez-Ortiz | 9f2d1b2 | 2018-01-10 11:33:50 +0100 | [diff] [blame] | 37 | #endif |