Simon Glass | 5e5c0cd | 2019-12-06 21:41:53 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright 2019 Google LLC |
| 4 | */ |
| 5 | |
| 6 | #define LOG_CATEGORY UCLASS_ACPI_PMC |
| 7 | |
| 8 | #include <common.h> |
Simon Glass | 5e5c0cd | 2019-12-06 21:41:53 -0700 | [diff] [blame] | 9 | #include <dm.h> |
| 10 | #include <log.h> |
Simon Glass | ec8ae8a | 2020-12-23 08:11:30 -0700 | [diff] [blame^] | 11 | #include <spl.h> |
Simon Glass | 5046109 | 2020-04-08 16:57:35 -0600 | [diff] [blame] | 12 | #include <acpi/acpi_s3.h> |
Simon Glass | e63ca97 | 2019-12-06 21:42:57 -0700 | [diff] [blame] | 13 | #ifdef CONFIG_X86 |
| 14 | #include <asm/intel_pinctrl.h> |
| 15 | #endif |
Simon Glass | 5e5c0cd | 2019-12-06 21:41:53 -0700 | [diff] [blame] | 16 | #include <asm/io.h> |
| 17 | #include <power/acpi_pmc.h> |
| 18 | |
Simon Glass | 5e5c0cd | 2019-12-06 21:41:53 -0700 | [diff] [blame] | 19 | struct tco_regs { |
| 20 | u32 tco_rld; |
| 21 | u32 tco_sts; |
| 22 | u32 tco1_cnt; |
| 23 | u32 tco_tmr; |
| 24 | }; |
| 25 | |
| 26 | enum { |
| 27 | TCO_STS_TIMEOUT = 1 << 3, |
| 28 | TCO_STS_SECOND_TO_STS = 1 << 17, |
| 29 | TCO1_CNT_HLT = 1 << 11, |
| 30 | }; |
| 31 | |
Simon Glass | e63ca97 | 2019-12-06 21:42:57 -0700 | [diff] [blame] | 32 | #ifdef CONFIG_X86 |
| 33 | static int gpe0_shift(struct acpi_pmc_upriv *upriv, int regnum) |
| 34 | { |
| 35 | return upriv->gpe0_dwx_shift_base + regnum * 4; |
| 36 | } |
| 37 | |
| 38 | int pmc_gpe_init(struct udevice *dev) |
| 39 | { |
| 40 | struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); |
| 41 | struct udevice *itss; |
| 42 | u32 *dw; |
| 43 | u32 gpio_cfg_mask; |
| 44 | u32 gpio_cfg; |
| 45 | int ret, i; |
| 46 | u32 mask; |
| 47 | |
| 48 | if (device_get_uclass_id(dev) != UCLASS_ACPI_PMC) |
| 49 | return log_msg_ret("uclass", -EPROTONOSUPPORT); |
| 50 | dw = upriv->gpe0_dw; |
| 51 | mask = upriv->gpe0_dwx_mask; |
| 52 | gpio_cfg_mask = 0; |
| 53 | for (i = 0; i < upriv->gpe0_count; i++) { |
| 54 | gpio_cfg_mask |= mask << gpe0_shift(upriv, i); |
| 55 | if (dw[i] & ~mask) |
| 56 | return log_msg_ret("Base GPE0 value", -EINVAL); |
| 57 | } |
| 58 | |
| 59 | /* |
| 60 | * Route the GPIOs to the GPE0 block. Determine that all values |
| 61 | * are different and if they aren't, use the reset values. |
| 62 | */ |
| 63 | if (dw[0] == dw[1] || dw[1] == dw[2]) { |
Simon Glass | ec8ae8a | 2020-12-23 08:11:30 -0700 | [diff] [blame^] | 64 | if (spl_phase() > PHASE_TPL) |
| 65 | log_info("PMC: Using default GPE route"); |
Simon Glass | e63ca97 | 2019-12-06 21:42:57 -0700 | [diff] [blame] | 66 | gpio_cfg = readl(upriv->gpe_cfg); |
| 67 | for (i = 0; i < upriv->gpe0_count; i++) |
| 68 | dw[i] = gpio_cfg >> gpe0_shift(upriv, i); |
| 69 | } else { |
| 70 | gpio_cfg = 0; |
| 71 | for (i = 0; i < upriv->gpe0_count; i++) |
| 72 | gpio_cfg |= dw[i] << gpe0_shift(upriv, i); |
| 73 | clrsetbits_le32(upriv->gpe_cfg, gpio_cfg_mask, gpio_cfg); |
| 74 | } |
| 75 | |
| 76 | /* Set the routes in the GPIO communities as well */ |
| 77 | ret = uclass_first_device_err(UCLASS_IRQ, &itss); |
| 78 | if (ret) |
| 79 | return log_msg_ret("Cannot find itss", ret); |
| 80 | pinctrl_route_gpe(itss, dw[0], dw[1], dw[2]); |
| 81 | |
| 82 | return 0; |
| 83 | } |
| 84 | #endif /* CONFIG_X86 */ |
| 85 | |
Simon Glass | 5e5c0cd | 2019-12-06 21:41:53 -0700 | [diff] [blame] | 86 | static void pmc_fill_pm_reg_info(struct udevice *dev) |
| 87 | { |
| 88 | struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); |
| 89 | int i; |
| 90 | |
| 91 | upriv->pm1_sts = inw(upriv->acpi_base + PM1_STS); |
| 92 | upriv->pm1_en = inw(upriv->acpi_base + PM1_EN); |
| 93 | upriv->pm1_cnt = inw(upriv->acpi_base + PM1_CNT); |
| 94 | |
| 95 | log_debug("pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", |
| 96 | upriv->pm1_sts, upriv->pm1_en, upriv->pm1_cnt); |
| 97 | |
| 98 | for (i = 0; i < GPE0_REG_MAX; i++) { |
| 99 | upriv->gpe0_sts[i] = inl(upriv->acpi_base + GPE0_STS + i * 4); |
| 100 | upriv->gpe0_en[i] = inl(upriv->acpi_base + GPE0_EN + i * 4); |
| 101 | log_debug("gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i, |
| 102 | upriv->gpe0_sts[i], i, upriv->gpe0_en[i]); |
| 103 | } |
| 104 | } |
| 105 | |
| 106 | int pmc_disable_tco_base(ulong tco_base) |
| 107 | { |
| 108 | struct tco_regs *regs = (struct tco_regs *)tco_base; |
| 109 | |
| 110 | debug("tco_base %lx = %x\n", (ulong)®s->tco1_cnt, TCO1_CNT_HLT); |
| 111 | setio_32(®s->tco1_cnt, TCO1_CNT_HLT); |
| 112 | |
| 113 | return 0; |
| 114 | } |
| 115 | |
| 116 | int pmc_init(struct udevice *dev) |
| 117 | { |
| 118 | const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev); |
| 119 | int ret; |
| 120 | |
| 121 | pmc_fill_pm_reg_info(dev); |
| 122 | if (!ops->init) |
| 123 | return -ENOSYS; |
| 124 | |
| 125 | ret = ops->init(dev); |
| 126 | if (ret) |
| 127 | return log_msg_ret("Failed to init pmc", ret); |
| 128 | |
| 129 | #ifdef DEBUG |
| 130 | pmc_dump_info(dev); |
| 131 | #endif |
| 132 | |
| 133 | return 0; |
| 134 | } |
| 135 | |
| 136 | int pmc_prev_sleep_state(struct udevice *dev) |
| 137 | { |
| 138 | struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); |
| 139 | const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev); |
| 140 | int prev_sleep_state = ACPI_S0; /* Default to S0 */ |
| 141 | |
| 142 | if (upriv->pm1_sts & WAK_STS) { |
| 143 | switch (acpi_sleep_from_pm1(upriv->pm1_cnt)) { |
| 144 | case ACPI_S3: |
| 145 | if (IS_ENABLED(HAVE_ACPI_RESUME)) |
| 146 | prev_sleep_state = ACPI_S3; |
| 147 | break; |
| 148 | case ACPI_S5: |
| 149 | prev_sleep_state = ACPI_S5; |
| 150 | break; |
| 151 | default: |
| 152 | break; |
| 153 | } |
| 154 | |
| 155 | /* Clear SLP_TYP */ |
| 156 | outl(upriv->pm1_cnt & ~SLP_TYP, upriv->acpi_base + PM1_CNT); |
| 157 | } |
| 158 | |
| 159 | if (!ops->prev_sleep_state) |
| 160 | return prev_sleep_state; |
| 161 | |
| 162 | return ops->prev_sleep_state(dev, prev_sleep_state); |
| 163 | } |
| 164 | |
| 165 | int pmc_disable_tco(struct udevice *dev) |
| 166 | { |
| 167 | const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev); |
| 168 | |
| 169 | pmc_fill_pm_reg_info(dev); |
| 170 | if (!ops->disable_tco) |
| 171 | return -ENOSYS; |
| 172 | |
| 173 | return ops->disable_tco(dev); |
| 174 | } |
| 175 | |
| 176 | int pmc_global_reset_set_enable(struct udevice *dev, bool enable) |
| 177 | { |
| 178 | const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev); |
| 179 | |
| 180 | if (!ops->global_reset_set_enable) |
| 181 | return -ENOSYS; |
| 182 | |
| 183 | return ops->global_reset_set_enable(dev, enable); |
| 184 | } |
| 185 | |
| 186 | void pmc_dump_info(struct udevice *dev) |
| 187 | { |
| 188 | struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); |
| 189 | int i; |
| 190 | |
| 191 | printf("Device: %s\n", dev->name); |
| 192 | printf("ACPI base %x, pmc_bar0 %p, pmc_bar2 %p, gpe_cfg %p\n", |
| 193 | upriv->acpi_base, upriv->pmc_bar0, upriv->pmc_bar2, |
| 194 | upriv->gpe_cfg); |
| 195 | printf("pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", |
| 196 | upriv->pm1_sts, upriv->pm1_en, upriv->pm1_cnt); |
| 197 | |
| 198 | for (i = 0; i < GPE0_REG_MAX; i++) { |
| 199 | printf("gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i, |
| 200 | upriv->gpe0_sts[i], i, upriv->gpe0_en[i]); |
| 201 | } |
| 202 | |
| 203 | printf("prsts: %08x\n", upriv->prsts); |
| 204 | printf("tco_sts: %04x %04x\n", upriv->tco1_sts, upriv->tco2_sts); |
| 205 | printf("gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n", |
| 206 | upriv->gen_pmcon1, upriv->gen_pmcon2, upriv->gen_pmcon3); |
| 207 | } |
| 208 | |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 209 | int pmc_ofdata_to_uc_plat(struct udevice *dev) |
Simon Glass | 5e5c0cd | 2019-12-06 21:41:53 -0700 | [diff] [blame] | 210 | { |
| 211 | struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); |
| 212 | int ret; |
| 213 | |
| 214 | ret = dev_read_u32(dev, "gpe0-dwx-mask", &upriv->gpe0_dwx_mask); |
| 215 | if (ret) |
| 216 | return log_msg_ret("no gpe0-dwx-mask", ret); |
| 217 | ret = dev_read_u32(dev, "gpe0-dwx-shift-base", |
| 218 | &upriv->gpe0_dwx_shift_base); |
| 219 | if (ret) |
| 220 | return log_msg_ret("no gpe0-dwx-shift-base", ret); |
| 221 | ret = dev_read_u32(dev, "gpe0-sts", &upriv->gpe0_sts_reg); |
| 222 | if (ret) |
| 223 | return log_msg_ret("no gpe0-sts", ret); |
| 224 | upriv->gpe0_sts_reg += upriv->acpi_base; |
| 225 | ret = dev_read_u32(dev, "gpe0-en", &upriv->gpe0_en_reg); |
| 226 | if (ret) |
| 227 | return log_msg_ret("no gpe0-en", ret); |
| 228 | upriv->gpe0_en_reg += upriv->acpi_base; |
| 229 | |
| 230 | return 0; |
| 231 | } |
| 232 | |
| 233 | UCLASS_DRIVER(acpi_pmc) = { |
| 234 | .id = UCLASS_ACPI_PMC, |
| 235 | .name = "power-mgr", |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 236 | .per_device_auto = sizeof(struct acpi_pmc_upriv), |
Simon Glass | 5e5c0cd | 2019-12-06 21:41:53 -0700 | [diff] [blame] | 237 | }; |