| Keerthy | 05d670e | 2021-04-23 11:27:33 -0500 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * K3: AM64 SoC definitions, structures etc. |
| 4 | * |
| 5 | * (C) Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ |
| 6 | */ |
| 7 | #ifndef __ASM_ARCH_AM64_HARDWARE_H |
| 8 | #define __ASM_ARCH_AM64_HARDWARE_H |
| 9 | |
| 10 | #include <config.h> |
| 11 | |
| 12 | #define CTRL_MMR0_BASE 0x43000000 |
| 13 | #define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) |
| 14 | |
| 15 | #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078 |
| 16 | #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 |
| 17 | |
| 18 | #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK 0x00000380 |
| 19 | #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7 |
| 20 | |
| 21 | #define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK 0x00001c00 |
| 22 | #define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10 |
| 23 | |
| 24 | #define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK 0x00002000 |
| 25 | #define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13 |
| 26 | |
| 27 | /* After the cfg mask and shifts have been applied */ |
| 28 | #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2 |
| 29 | #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x04 |
| 30 | |
| 31 | /* |
| 32 | * The CTRL_MMR memory space is divided into several equally-spaced |
| 33 | * partitions, so defining the partition size allows us to determine |
| 34 | * register addresses common to those partitions. |
| 35 | */ |
| 36 | #define CTRL_MMR0_PARTITION_SIZE 0x4000 |
| 37 | |
| 38 | /* |
| 39 | * CTRL_MMR lock/kick-mechanism shared register definitions. |
| 40 | */ |
| 41 | #define CTRLMMR_LOCK_KICK0 0x01008 |
| 42 | #define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 |
| 43 | #define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) |
| 44 | #define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 |
| 45 | #define CTRLMMR_LOCK_KICK1 0x0100c |
| 46 | #define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a |
| 47 | |
| 48 | #endif /* __ASM_ARCH_DRA8_HARDWARE_H */ |