Vignesh Raghavendra | a555286 | 2020-07-07 13:43:33 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
Nishanth Menon | eaa39c6 | 2023-11-01 15:56:03 -0500 | [diff] [blame^] | 3 | * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com |
Vignesh Raghavendra | a555286 | 2020-07-07 13:43:33 +0530 | [diff] [blame] | 4 | * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> |
| 5 | */ |
| 6 | |
| 7 | #include <linux/kernel.h> |
| 8 | |
| 9 | #include "k3-psil-priv.h" |
| 10 | |
| 11 | #define PSIL_ETHERNET(x) \ |
| 12 | { \ |
| 13 | .thread_id = x, \ |
| 14 | .ep_config = { \ |
| 15 | .ep_type = PSIL_EP_NATIVE, \ |
| 16 | .pkt_mode = 1, \ |
| 17 | .needs_epib = 1, \ |
| 18 | .psd_size = 16, \ |
| 19 | }, \ |
| 20 | } |
| 21 | |
| 22 | /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ |
| 23 | static struct psil_ep am654_src_ep_map[] = { |
| 24 | /* PRU_ICSSG0 */ |
| 25 | PSIL_ETHERNET(0x4100), |
| 26 | PSIL_ETHERNET(0x4101), |
| 27 | PSIL_ETHERNET(0x4102), |
| 28 | PSIL_ETHERNET(0x4103), |
| 29 | /* PRU_ICSSG1 */ |
| 30 | PSIL_ETHERNET(0x4200), |
| 31 | PSIL_ETHERNET(0x4201), |
| 32 | PSIL_ETHERNET(0x4202), |
| 33 | PSIL_ETHERNET(0x4203), |
| 34 | /* PRU_ICSSG2 */ |
| 35 | PSIL_ETHERNET(0x4300), |
| 36 | PSIL_ETHERNET(0x4301), |
| 37 | PSIL_ETHERNET(0x4302), |
| 38 | PSIL_ETHERNET(0x4303), |
| 39 | /* CPSW0 */ |
| 40 | PSIL_ETHERNET(0x7000), |
| 41 | }; |
| 42 | |
| 43 | /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ |
| 44 | static struct psil_ep am654_dst_ep_map[] = { |
| 45 | /* PRU_ICSSG0 */ |
| 46 | PSIL_ETHERNET(0xc100), |
Vignesh Raghavendra | 18f39de | 2021-05-10 20:06:05 +0530 | [diff] [blame] | 47 | /* PSIL: 0xc101 - 0xc103 unused */ |
Vignesh Raghavendra | a555286 | 2020-07-07 13:43:33 +0530 | [diff] [blame] | 48 | PSIL_ETHERNET(0xc104), |
Vignesh Raghavendra | 18f39de | 2021-05-10 20:06:05 +0530 | [diff] [blame] | 49 | /* PSIL: 0xc105 - 0xc107 unused */ |
Vignesh Raghavendra | a555286 | 2020-07-07 13:43:33 +0530 | [diff] [blame] | 50 | /* PRU_ICSSG1 */ |
| 51 | PSIL_ETHERNET(0xc200), |
Vignesh Raghavendra | 18f39de | 2021-05-10 20:06:05 +0530 | [diff] [blame] | 52 | /* PSIL: 0xc201 - 0xc203 unused */ |
Vignesh Raghavendra | a555286 | 2020-07-07 13:43:33 +0530 | [diff] [blame] | 53 | PSIL_ETHERNET(0xc204), |
Vignesh Raghavendra | 18f39de | 2021-05-10 20:06:05 +0530 | [diff] [blame] | 54 | /* PSIL: 0xc205 - 0xc207 unused */ |
Vignesh Raghavendra | a555286 | 2020-07-07 13:43:33 +0530 | [diff] [blame] | 55 | /* PRU_ICSSG2 */ |
| 56 | PSIL_ETHERNET(0xc300), |
Vignesh Raghavendra | 18f39de | 2021-05-10 20:06:05 +0530 | [diff] [blame] | 57 | /* PSIL: 0xc301 - 0xc303 unused */ |
Vignesh Raghavendra | a555286 | 2020-07-07 13:43:33 +0530 | [diff] [blame] | 58 | PSIL_ETHERNET(0xc304), |
Vignesh Raghavendra | 18f39de | 2021-05-10 20:06:05 +0530 | [diff] [blame] | 59 | /* PSIL: 0xc305 - 0xc307 unused */ |
Vignesh Raghavendra | a555286 | 2020-07-07 13:43:33 +0530 | [diff] [blame] | 60 | /* CPSW0 */ |
| 61 | PSIL_ETHERNET(0xf000), |
Vignesh Raghavendra | 18f39de | 2021-05-10 20:06:05 +0530 | [diff] [blame] | 62 | /* PSIL: 0xf001 - 0xf007 unused */ |
Vignesh Raghavendra | a555286 | 2020-07-07 13:43:33 +0530 | [diff] [blame] | 63 | }; |
| 64 | |
| 65 | struct psil_ep_map am654_ep_map = { |
| 66 | .name = "am654", |
| 67 | .src = am654_src_ep_map, |
| 68 | .src_count = ARRAY_SIZE(am654_src_ep_map), |
| 69 | .dst = am654_dst_ep_map, |
| 70 | .dst_count = ARRAY_SIZE(am654_dst_ep_map), |
| 71 | }; |