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git01.mediatek.com / filogic / uboot / eaa39c6960f19c3c7f38641db379ee5d13016721 / . / arch / arm / dts / am335x-pxm2.dtsi
blob: a49560924b3dabd0a1d6903262b93c957ef6ab31 [file] [log] [blame]
Heiko Schocher107ef972016-06-13 15:16:01 +0200[diff] [blame]1/*
2 * Copyright (C) 2014 DENX Software Engineering GmbH
3 * Heiko Schocher <hs@denx.de>
4 *
5 * Based on:
Nishanth Menoneaa39c62023-11-01 15:56:03 -0500[diff] [blame^]6 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
Heiko Schocher107ef972016-06-13 15:16:01 +0200[diff] [blame]7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include "am33xx.dtsi"
14#include <dt-bindings/input/input.h>
15
16/ {
17 chosen {
18 stdout-path = &uart0;
19 tick-timer = &timer2;
20 };
21
22 cpus {
23 cpu@0 {
24 cpu0-supply = <&vdd1_reg>;
25 };
26 };
27
28 backlight0: backlight {
29 compatible = "pwm-backlight";
30 pwms = <&ecap0 0 50000 0>;
31 brightness-levels = <0 2 5 7 10 12 15 17 20 22 25 28 30 33 35
32 38 40 43 45 48 51 53 56 58 61 63 66 68 71
33 73 76 79 81 84 86 89 91 94 96 99 102 104
34 107 109 112 114 117 119 122 124 127 130
35 132 135 137 140 142 145 147 150 153 155
36 158 160 163 165 168 170 173 175 178 181
37 183 186 188 191 193 196 198 201 204 206
38 209 211 214 216 219 221 224 226 229 232
39 234 237 239 242 244 247 249 252 255>;
40 default-brightness-level = <80>;
41 power-supply = <&backlight_reg>;
42 enable-gpios = <&gpio3 16 0>;
43 };
44
45 backlight_reg: fixedregulator0 {
46 compatible = "regulator-fixed";
47 regulator-name = "backlight_reg";
48 regulator-boot-on;
49 };
50
51 gpio_keys: restart-keys {
52 compatible = "gpio-keys";
Heiko Schocher107ef972016-06-13 15:16:01 +0200[diff] [blame]53 autorepeat;
54
55 restart0 {
56 label = "restart";
57 linux,code = <KEY_RESTART>;
58 gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
59 gpio-key,wakeup;
60 };
61 };
62
63 leds {
64 compatible = "gpio-leds";
65
66 led_blue {
67 label = "blue";
68 gpios = <&gpio3 20 0>;
69 };
70 led_green {
71 label = "green";
72 gpios = <&gpio1 31 0>;
73 };
74 led_red {
75 label = "red";
76 gpios = <&gpio3 21 0>;
77 };
78 };
79
80 memory {
81 device_type = "memory";
82 reg = <0x80000000 0x10000000>; /* 256 MB */
83 };
84
85 reg_lcd_3v3: fixedregulator1 {
86 compatible = "regulator-gpio";
87 regulator-name = "lcd-3v3";
88 regulator-min-microvolt = <1800000>;
89 regulator-max-microvolt = <3300000>;
90 regulator-type = "voltage";
91 startup-delay-us = <100>;
92 states = <1800000 0x1
93 2900000 0x0>;
94 enable-at-boot;
95 gpios = <&gpio3 19 0>;
96 enable-active-high;
97 };
98
99 vbat: fixedregulator2 {
100 compatible = "regulator-fixed";
101 regulator-name = "vbat";
102 regulator-min-microvolt = <5000000>;
103 regulator-max-microvolt = <5000000>;
104 regulator-boot-on;
105 };
106
107 vmmc: fixedregulator3 {
108 compatible = "regulator-fixed";
109 regulator-name = "vmmc";
110 regulator-min-microvolt = <3300000>;
111 regulator-max-microvolt = <3300000>;
112 };
113};
114
115&cppi41dma {
116 status = "okay";
117};
118
119&cpsw_emac0 {
Grygorii Strashkoa6f37dc2019-08-31 10:30:34 +0300[diff] [blame]120 phy-handle = <&ethphy0>;
Heiko Schocher107ef972016-06-13 15:16:01 +0200[diff] [blame]121 phy-mode = "rgmii-txid";
122};
123
124&cpsw_emac1 {
Grygorii Strashkoa6f37dc2019-08-31 10:30:34 +0300[diff] [blame]125 phy-handle = <&ethphy1>;
Heiko Schocher107ef972016-06-13 15:16:01 +0200[diff] [blame]126 phy-mode = "rgmii-txid";
127};
128
129&davinci_mdio {
130 pinctrl-names = "default", "sleep";
131 pinctrl-0 = <&davinci_mdio_default>;
132 pinctrl-1 = <&davinci_mdio_sleep>;
133 status = "okay";
Grygorii Strashkoa6f37dc2019-08-31 10:30:34 +0300[diff] [blame]134
135 ethphy0: ethernet-phy@0 {
136 reg = <0>;
137 };
138
139 ethphy1: ethernet-phy@1 {
140 reg = <1>;
141 };
Heiko Schocher107ef972016-06-13 15:16:01 +0200[diff] [blame]142};
143
144&elm {
145 status = "okay";
146};
147
148&epwmss0 {
149 status = "okay";
150
Andrew Davisa45320d2023-04-11 13:25:05 -0500[diff] [blame]151 ecap0: pwm@100 {
Heiko Schocher107ef972016-06-13 15:16:01 +0200[diff] [blame]152 status = "okay";
153 pinctrl-names = "default";
154 pinctrl-0 = <&ecap0_pins>;
155 };
156};
157
158&gpmc {
159 pinctrl-names = "default";
160 pinctrl-0 = <&nandflash_pins>;
161 status = "okay";
162
163 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
164
165 nand@0,0 {
166 reg = <0 0 0>; /* CS0, offset 0 */
167 nand-bus-width = <8>;
168 ti,nand-ecc-opt = "bch8";
169 gpmc,device-nand = "true";
170 gpmc,device-width = <1>;
171 gpmc,sync-clk-ps = <0>;
172 gpmc,cs-on-ns = <0>;
173 gpmc,cs-rd-off-ns = <44>;
174 gpmc,cs-wr-off-ns = <44>;
175 gpmc,adv-on-ns = <6>;
176 gpmc,adv-rd-off-ns = <34>;
177 gpmc,adv-wr-off-ns = <44>;
178 gpmc,we-on-ns = <0>;
179 gpmc,we-off-ns = <40>;
180 gpmc,oe-on-ns = <0>;
181 gpmc,oe-off-ns = <54>;
182 gpmc,access-ns = <64>;
183 gpmc,rd-cycle-ns = <82>;
184 gpmc,wr-cycle-ns = <82>;
185 gpmc,wait-on-read = "true";
186 gpmc,wait-on-write = "true";
187 gpmc,bus-turnaround-ns = <0>;
188 gpmc,cycle2cycle-delay-ns = <0>;
189 gpmc,clk-activation-ns = <0>;
190 gpmc,wait-monitoring-ns = <0>;
191 gpmc,wr-access-ns = <40>;
192 gpmc,wr-data-mux-bus-ns = <0>;
193
194 #address-cells = <1>;
195 #size-cells = <1>;
196 elm_id = <&elm>;
197 };
198};
199
200&i2c0 {
201 pinctrl-names = "default";
202 pinctrl-0 = <&i2c0_pins>;
203 clock-frequency = <400000>;
204 status = "okay";
205
206 tps: tps@2d {
207 reg = <0x2d>;
208 };
209 eeprom: eeprom@50 {
210 compatible = "atmel,24c128";
211 reg = <0x50>;
212 pagesize = <32>;
213 };
214};
215
216&i2c1 {
217 pinctrl-names = "default";
218 pinctrl-0 = <&i2c1_pins>;
219 clock-frequency = <100000>;
220 status = "okay";
221
222 tsl2563: tsl2563@49 {
223 compatible = "amstaos,tsl2563";
224 reg = <0x49>;
225 };
226};
227
228&i2c2 {
229 pinctrl-names = "default";
230 pinctrl-0 = <&i2c2_pins>;
231 clock-frequency = <100000>;
232 status = "okay";
233
234 egalax_ts@04 {
235 compatible = "eeti,egalax_ts";
236 reg = <0x04>;
237 interrupt-parent = <&gpio1>;
238 interrupts = <24 2>;
239 wakeup-gpios = <&gpio1 25 0>;
240 };
241};
242
243&lcdc {
244 status = "okay";
245};
246
247&mac {
248 pinctrl-names = "default", "sleep";
249 pinctrl-0 = <&cpsw_default>;
250 pinctrl-1 = <&cpsw_sleep>;
251 status = "okay";
252};
253
254&mmc1 {
255 vmmc-supply = <&vmmc>;
256 bus-width = <4>;
257 cd-gpios = <&gpio0 6 0>;
258 wp-gpios = <&gpio3 18 0>;
259 status = "okay";
260};
261
262&phy_sel {
263 rgmii-no-delay;
264};
265
266#include "tps65910.dtsi"
267
268&tps {
269 vcc1-supply = <&vbat>;
270 vcc2-supply = <&vbat>;
271 vcc3-supply = <&vbat>;
272 vcc4-supply = <&vbat>;
273 vcc5-supply = <&vbat>;
274 vcc6-supply = <&vbat>;
275 vcc7-supply = <&vbat>;
276 vccio-supply = <&vbat>;
277
278 regulators {
279 vrtc_reg: regulator@0 {
280 regulator-always-on;
281 };
282
283 vio_reg: regulator@1 {
284 regulator-always-on;
285 };
286
287 vdd1_reg: regulator@2 {
288 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
289 regulator-name = "vdd_mpu";
290 regulator-min-microvolt = <912500>;
291 regulator-max-microvolt = <1312500>;
292 regulator-boot-on;
293 regulator-always-on;
294 };
295
296 vdd2_reg: regulator@3 {
297 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
298 regulator-name = "vdd_core";
299 regulator-min-microvolt = <912500>;
300 regulator-max-microvolt = <1150000>;
301 regulator-boot-on;
302 regulator-always-on;
303 };
304
305 vdd3_reg: regulator@4 {
306 regulator-always-on;
307 };
308
309 vdig1_reg: regulator@5 {
310 regulator-always-on;
311 };
312
313 vdig2_reg: regulator@6 {
314 regulator-always-on;
315 };
316
317 vpll_reg: regulator@7 {
318 regulator-always-on;
319 };
320
321 vdac_reg: regulator@8 {
322 regulator-always-on;
323 };
324
325 vaux1_reg: regulator@9 {
326 regulator-always-on;
327 };
328
329 vaux2_reg: regulator@10 {
330 regulator-always-on;
331 };
332
333 vaux33_reg: regulator@11 {
334 regulator-always-on;
335 };
336
337 vmmc_reg: regulator@12 {
338 regulator-min-microvolt = <1800000>;
339 regulator-max-microvolt = <3300000>;
340 regulator-always-on;
341 };
342 };
343};
344
345&uart0 {
346 pinctrl-names = "default";
347 pinctrl-0 = <&uart0_pins>;
348
349 status = "okay";
350};
351
352&usb {
353 status = "okay";
354};
355
356&usb_ctrl_mod {
357 status = "okay";
358};
359
360&usb0 {
361 status = "okay";
362};
363
364&usb1 {
365 dr_mode = "host";
366 status = "okay";
367};
368
369&usb0_phy {
370 status = "okay";
371};
372
373&usb1_phy {
374 status = "okay";
375};
376
377&am33xx_pinmux {
378 pinctrl-names = "default";
379 pinctrl-0 = <&clkout2_pin &gpio_pin>;
380
381 clkout2_pin: pinmux_clkout2_pin {
382 pinctrl-single,pins = <
383 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
384 >;
385 };
386
387 cpsw_default: cpsw_default {
388 pinctrl-single,pins = <
389 /* Slave 1 */
390 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
391 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
392 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
393 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
394 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
395 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
396 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
397 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
398 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
399 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
400 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
401 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
402 >;
403 };
404
405 cpsw_sleep: cpsw_sleep {
406 pinctrl-single,pins = <
407 /* Slave 1 reset value */
408 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
409 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
410 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
411 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
412 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
413 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
414 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
415 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
416 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
417 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
418 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
419 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
420 >;
421 };
422
423 davinci_mdio_default: davinci_mdio_default {
424 pinctrl-single,pins = <
425 /* MDIO */
426 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
427 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
428 >;
429 };
430
431 davinci_mdio_sleep: davinci_mdio_sleep {
432 pinctrl-single,pins = <
433 /* MDIO reset value */
434 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
435 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
436 >;
437 };
438
439 ecap0_pins: ecap_pins {
440 pinctrl-single,pins = <
441 0x198 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mcasp0_axr0.gpio3_16 Backlight enable */
442 0x164 (MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
443 >;
444 };
445
446
447 gpio_pin: gpio_pin {
448 pinctrl-single,pins = <
449 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 touch reset */
450 0x60 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 touch irq */
451 0x64 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a9.gpio1_25 touch power */
452 0x6c (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a11.gpio1_27 pad14 to DFU */
453 0x21c (MUX_MODE0) /* usb0_drvvbus */
454 0x234 (MUX_MODE0) /* usb1_drvvbus */
455 0x1a0 (PIN_INPUT_PULLUP | MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */
456 0x160 (PIN_INPUT_PULLUP | MUX_MODE5) /* spi0_cs1.mmc0_sdcd */
457 >;
458 };
459
460 i2c0_pins: pinmux_i2c0_pins {
461 pinctrl-single,pins = <
462 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
463 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
464 >;
465 };
466
467 i2c1_pins: pinmux_i2c1_pins {
468 pinctrl-single,pins = <
469 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
470 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
471 >;
472 };
473
474 i2c2_pins: pinmux_i2c2_pins {
475 pinctrl-single,pins = <
476 0x150 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_sclk.i2c2_sda */
477 0x154 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c2_scl */
478 >;
479 };
480
481 lcd_pins_s0: lcd_pins_s0 {
482 pinctrl-single,pins = <
483 0x20 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
484 0x24 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
485 0x28 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
486 0x2c (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
487 0x30 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
488 0x34 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
489 0x38 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
490 0x3c (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
491 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
492 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
493 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
494 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
495 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
496 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
497 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
498 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
499 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
500 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
501 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
502 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
503 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
504 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
505 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
506 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
507 0xe0 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */
508 0xe4 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */
509 0xe8 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */
510 0xec (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
511 0x194 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mcasp0_fsx.gpio3_15 LCD enable */
512 >;
513 };
514
515 nandflash_pins: pinmux_nandflash_pins {
516 pinctrl-single,pins = <
517 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
518 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
519 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
520 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
521 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
522 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
523 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
524 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
525 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
526 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
527 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
528 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
529 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
530 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
531 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
532 >;
533 };
534
535 uart0_pins: pinmux_uart0_pins {
536 pinctrl-single,pins = <
537 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
538 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
539 >;
540 };
541};
542
543&wdt2 {
544 wdt-keep-enabled;
545};