Kuo-Jung Su | 78ba07d | 2013-05-15 15:29:24 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Faraday USB 2.0 OTG Controller |
| 3 | * |
| 4 | * (C) Copyright 2010 Faraday Technology |
| 5 | * Dante Su <dantesu@faraday-tech.com> |
| 6 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
Kuo-Jung Su | 78ba07d | 2013-05-15 15:29:24 +0800 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <common.h> |
| 11 | #include <command.h> |
| 12 | #include <config.h> |
| 13 | #include <net.h> |
| 14 | #include <malloc.h> |
| 15 | #include <asm/io.h> |
| 16 | #include <asm/errno.h> |
| 17 | #include <linux/types.h> |
| 18 | #include <linux/usb/ch9.h> |
| 19 | #include <linux/usb/gadget.h> |
| 20 | |
| 21 | #include <usb/fotg210.h> |
| 22 | |
| 23 | #define CFG_NUM_ENDPOINTS 4 |
| 24 | #define CFG_EP0_MAX_PACKET_SIZE 64 |
| 25 | #define CFG_EPX_MAX_PACKET_SIZE 512 |
| 26 | |
| 27 | #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 2) /* 250 ms */ |
| 28 | |
| 29 | struct fotg210_chip; |
| 30 | |
| 31 | struct fotg210_ep { |
| 32 | struct usb_ep ep; |
| 33 | |
| 34 | uint maxpacket; |
| 35 | uint id; |
| 36 | uint stopped; |
| 37 | |
| 38 | struct list_head queue; |
| 39 | struct fotg210_chip *chip; |
| 40 | const struct usb_endpoint_descriptor *desc; |
| 41 | }; |
| 42 | |
| 43 | struct fotg210_request { |
| 44 | struct usb_request req; |
| 45 | struct list_head queue; |
| 46 | struct fotg210_ep *ep; |
| 47 | }; |
| 48 | |
| 49 | struct fotg210_chip { |
| 50 | struct usb_gadget gadget; |
| 51 | struct usb_gadget_driver *driver; |
| 52 | struct fotg210_regs *regs; |
| 53 | uint8_t irq; |
| 54 | uint16_t addr; |
| 55 | int pullup; |
| 56 | enum usb_device_state state; |
| 57 | struct fotg210_ep ep[1 + CFG_NUM_ENDPOINTS]; |
| 58 | }; |
| 59 | |
| 60 | static struct usb_endpoint_descriptor ep0_desc = { |
| 61 | .bLength = sizeof(struct usb_endpoint_descriptor), |
| 62 | .bDescriptorType = USB_DT_ENDPOINT, |
| 63 | .bEndpointAddress = USB_DIR_IN, |
| 64 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, |
| 65 | }; |
| 66 | |
| 67 | static inline int fifo_to_ep(struct fotg210_chip *chip, int id, int in) |
| 68 | { |
| 69 | return (id < 0) ? 0 : ((id & 0x03) + 1); |
| 70 | } |
| 71 | |
| 72 | static inline int ep_to_fifo(struct fotg210_chip *chip, int id) |
| 73 | { |
| 74 | return (id <= 0) ? -1 : ((id - 1) & 0x03); |
| 75 | } |
| 76 | |
| 77 | static inline int ep_reset(struct fotg210_chip *chip, uint8_t ep_addr) |
| 78 | { |
| 79 | int ep = ep_addr & USB_ENDPOINT_NUMBER_MASK; |
| 80 | struct fotg210_regs *regs = chip->regs; |
| 81 | |
| 82 | if (ep_addr & USB_DIR_IN) { |
| 83 | /* reset endpoint */ |
| 84 | setbits_le32(®s->iep[ep - 1], IEP_RESET); |
| 85 | mdelay(1); |
| 86 | clrbits_le32(®s->iep[ep - 1], IEP_RESET); |
| 87 | /* clear endpoint stall */ |
| 88 | clrbits_le32(®s->iep[ep - 1], IEP_STALL); |
| 89 | } else { |
| 90 | /* reset endpoint */ |
| 91 | setbits_le32(®s->oep[ep - 1], OEP_RESET); |
| 92 | mdelay(1); |
| 93 | clrbits_le32(®s->oep[ep - 1], OEP_RESET); |
| 94 | /* clear endpoint stall */ |
| 95 | clrbits_le32(®s->oep[ep - 1], OEP_STALL); |
| 96 | } |
| 97 | |
| 98 | return 0; |
| 99 | } |
| 100 | |
| 101 | static int fotg210_reset(struct fotg210_chip *chip) |
| 102 | { |
| 103 | struct fotg210_regs *regs = chip->regs; |
| 104 | uint32_t i; |
| 105 | |
| 106 | chip->state = USB_STATE_POWERED; |
| 107 | |
| 108 | /* chip enable */ |
| 109 | writel(DEVCTRL_EN, ®s->dev_ctrl); |
| 110 | |
| 111 | /* device address reset */ |
| 112 | chip->addr = 0; |
| 113 | writel(0, ®s->dev_addr); |
| 114 | |
| 115 | /* set idle counter to 7ms */ |
| 116 | writel(7, ®s->idle); |
| 117 | |
| 118 | /* disable all interrupts */ |
| 119 | writel(IMR_MASK, ®s->imr); |
| 120 | writel(GIMR_MASK, ®s->gimr); |
| 121 | writel(GIMR0_MASK, ®s->gimr0); |
| 122 | writel(GIMR1_MASK, ®s->gimr1); |
| 123 | writel(GIMR2_MASK, ®s->gimr2); |
| 124 | |
| 125 | /* clear interrupts */ |
| 126 | writel(ISR_MASK, ®s->isr); |
| 127 | writel(0, ®s->gisr); |
| 128 | writel(0, ®s->gisr0); |
| 129 | writel(0, ®s->gisr1); |
| 130 | writel(0, ®s->gisr2); |
| 131 | |
| 132 | /* chip reset */ |
| 133 | setbits_le32(®s->dev_ctrl, DEVCTRL_RESET); |
| 134 | mdelay(10); |
| 135 | if (readl(®s->dev_ctrl) & DEVCTRL_RESET) { |
| 136 | printf("fotg210: chip reset failed\n"); |
| 137 | return -1; |
| 138 | } |
| 139 | |
| 140 | /* CX FIFO reset */ |
| 141 | setbits_le32(®s->cxfifo, CXFIFO_CXFIFOCLR); |
| 142 | mdelay(10); |
| 143 | if (readl(®s->cxfifo) & CXFIFO_CXFIFOCLR) { |
| 144 | printf("fotg210: ep0 fifo reset failed\n"); |
| 145 | return -1; |
| 146 | } |
| 147 | |
| 148 | /* create static ep-fifo map (EP1 <-> FIFO0, EP2 <-> FIFO1 ...) */ |
| 149 | writel(EPMAP14_DEFAULT, ®s->epmap14); |
| 150 | writel(EPMAP58_DEFAULT, ®s->epmap58); |
| 151 | writel(FIFOMAP_DEFAULT, ®s->fifomap); |
| 152 | writel(0, ®s->fifocfg); |
| 153 | for (i = 0; i < 8; ++i) { |
| 154 | writel(CFG_EPX_MAX_PACKET_SIZE, ®s->iep[i]); |
| 155 | writel(CFG_EPX_MAX_PACKET_SIZE, ®s->oep[i]); |
| 156 | } |
| 157 | |
| 158 | /* FIFO reset */ |
| 159 | for (i = 0; i < 4; ++i) { |
| 160 | writel(FIFOCSR_RESET, ®s->fifocsr[i]); |
| 161 | mdelay(10); |
| 162 | if (readl(®s->fifocsr[i]) & FIFOCSR_RESET) { |
| 163 | printf("fotg210: fifo%d reset failed\n", i); |
| 164 | return -1; |
| 165 | } |
| 166 | } |
| 167 | |
| 168 | /* enable only device interrupt and triggered at level-high */ |
| 169 | writel(IMR_IRQLH | IMR_HOST | IMR_OTG, ®s->imr); |
| 170 | writel(ISR_MASK, ®s->isr); |
| 171 | /* disable EP0 IN/OUT interrupt */ |
| 172 | writel(GIMR0_CXOUT | GIMR0_CXIN, ®s->gimr0); |
| 173 | /* disable EPX IN+SPK+OUT interrupts */ |
| 174 | writel(GIMR1_MASK, ®s->gimr1); |
| 175 | /* disable wakeup+idle+dma+zlp interrupts */ |
| 176 | writel(GIMR2_WAKEUP | GIMR2_IDLE | GIMR2_DMAERR | GIMR2_DMAFIN |
| 177 | | GIMR2_ZLPRX | GIMR2_ZLPTX, ®s->gimr2); |
| 178 | /* enable all group interrupt */ |
| 179 | writel(0, ®s->gimr); |
| 180 | |
| 181 | /* suspend delay = 3 ms */ |
| 182 | writel(3, ®s->idle); |
| 183 | |
| 184 | /* turn-on device interrupts */ |
| 185 | setbits_le32(®s->dev_ctrl, DEVCTRL_GIRQ_EN); |
| 186 | |
| 187 | return 0; |
| 188 | } |
| 189 | |
| 190 | static inline int fotg210_cxwait(struct fotg210_chip *chip, uint32_t mask) |
| 191 | { |
| 192 | struct fotg210_regs *regs = chip->regs; |
| 193 | int ret = -1; |
| 194 | ulong ts; |
| 195 | |
| 196 | for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { |
| 197 | if ((readl(®s->cxfifo) & mask) != mask) |
| 198 | continue; |
| 199 | ret = 0; |
| 200 | break; |
| 201 | } |
| 202 | |
| 203 | if (ret) |
| 204 | printf("fotg210: cx/ep0 timeout\n"); |
| 205 | |
| 206 | return ret; |
| 207 | } |
| 208 | |
| 209 | static int fotg210_dma(struct fotg210_ep *ep, struct fotg210_request *req) |
| 210 | { |
| 211 | struct fotg210_chip *chip = ep->chip; |
| 212 | struct fotg210_regs *regs = chip->regs; |
| 213 | uint32_t tmp, ts; |
| 214 | uint8_t *buf = req->req.buf + req->req.actual; |
| 215 | uint32_t len = req->req.length - req->req.actual; |
| 216 | int fifo = ep_to_fifo(chip, ep->id); |
| 217 | int ret = -EBUSY; |
| 218 | |
| 219 | /* 1. init dma buffer */ |
| 220 | if (len > ep->maxpacket) |
| 221 | len = ep->maxpacket; |
| 222 | |
| 223 | /* 2. wait for dma ready (hardware) */ |
| 224 | for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { |
| 225 | if (!(readl(®s->dma_ctrl) & DMACTRL_START)) { |
| 226 | ret = 0; |
| 227 | break; |
| 228 | } |
| 229 | } |
| 230 | if (ret) { |
| 231 | printf("fotg210: dma busy\n"); |
| 232 | req->req.status = ret; |
| 233 | return ret; |
| 234 | } |
| 235 | |
| 236 | /* 3. DMA target setup */ |
| 237 | if (ep->desc->bEndpointAddress & USB_DIR_IN) |
| 238 | flush_dcache_range((ulong)buf, (ulong)buf + len); |
| 239 | else |
| 240 | invalidate_dcache_range((ulong)buf, (ulong)buf + len); |
| 241 | |
| 242 | writel(virt_to_phys(buf), ®s->dma_addr); |
| 243 | |
| 244 | if (ep->desc->bEndpointAddress & USB_DIR_IN) { |
| 245 | if (ep->id == 0) { |
| 246 | /* Wait until cx/ep0 fifo empty */ |
| 247 | fotg210_cxwait(chip, CXFIFO_CXFIFOE); |
| 248 | writel(DMAFIFO_CX, ®s->dma_fifo); |
| 249 | } else { |
| 250 | /* Wait until epx fifo empty */ |
| 251 | fotg210_cxwait(chip, CXFIFO_FIFOE(fifo)); |
| 252 | writel(DMAFIFO_FIFO(fifo), ®s->dma_fifo); |
| 253 | } |
| 254 | writel(DMACTRL_LEN(len) | DMACTRL_MEM2FIFO, ®s->dma_ctrl); |
| 255 | } else { |
| 256 | uint32_t blen; |
| 257 | |
| 258 | if (ep->id == 0) { |
| 259 | writel(DMAFIFO_CX, ®s->dma_fifo); |
| 260 | do { |
| 261 | blen = CXFIFO_BYTES(readl(®s->cxfifo)); |
| 262 | } while (blen < len); |
| 263 | } else { |
| 264 | writel(DMAFIFO_FIFO(fifo), ®s->dma_fifo); |
| 265 | blen = FIFOCSR_BYTES(readl(®s->fifocsr[fifo])); |
| 266 | } |
| 267 | len = (len < blen) ? len : blen; |
| 268 | writel(DMACTRL_LEN(len) | DMACTRL_FIFO2MEM, ®s->dma_ctrl); |
| 269 | } |
| 270 | |
| 271 | /* 4. DMA start */ |
| 272 | setbits_le32(®s->dma_ctrl, DMACTRL_START); |
| 273 | |
| 274 | /* 5. DMA wait */ |
| 275 | ret = -EBUSY; |
| 276 | for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { |
| 277 | tmp = readl(®s->gisr2); |
| 278 | /* DMA complete */ |
| 279 | if (tmp & GISR2_DMAFIN) { |
| 280 | ret = 0; |
| 281 | break; |
| 282 | } |
| 283 | /* DMA error */ |
| 284 | if (tmp & GISR2_DMAERR) { |
| 285 | printf("fotg210: dma error\n"); |
| 286 | break; |
| 287 | } |
| 288 | /* resume, suspend, reset */ |
| 289 | if (tmp & (GISR2_RESUME | GISR2_SUSPEND | GISR2_RESET)) { |
| 290 | printf("fotg210: dma reset by host\n"); |
| 291 | break; |
| 292 | } |
| 293 | } |
| 294 | |
| 295 | /* 7. DMA target reset */ |
| 296 | if (ret) |
| 297 | writel(DMACTRL_ABORT | DMACTRL_CLRFF, ®s->dma_ctrl); |
| 298 | |
| 299 | writel(0, ®s->gisr2); |
| 300 | writel(0, ®s->dma_fifo); |
| 301 | |
| 302 | req->req.status = ret; |
| 303 | if (!ret) |
| 304 | req->req.actual += len; |
| 305 | else |
| 306 | printf("fotg210: ep%d dma error(code=%d)\n", ep->id, ret); |
| 307 | |
| 308 | return len; |
| 309 | } |
| 310 | |
| 311 | /* |
| 312 | * result of setup packet |
| 313 | */ |
| 314 | #define CX_IDLE 0 |
| 315 | #define CX_FINISH 1 |
| 316 | #define CX_STALL 2 |
| 317 | |
| 318 | static void fotg210_setup(struct fotg210_chip *chip) |
| 319 | { |
| 320 | int id, ret = CX_IDLE; |
| 321 | uint32_t tmp[2]; |
| 322 | struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)tmp; |
| 323 | struct fotg210_regs *regs = chip->regs; |
| 324 | |
| 325 | /* |
| 326 | * If this is the first Cx 8 byte command, |
| 327 | * we can now query USB mode (high/full speed; USB 2.0/USB 1.0) |
| 328 | */ |
| 329 | if (chip->state == USB_STATE_POWERED) { |
| 330 | chip->state = USB_STATE_DEFAULT; |
| 331 | if (readl(®s->otgcsr) & OTGCSR_DEV_B) { |
| 332 | /* Mini-B */ |
| 333 | if (readl(®s->dev_ctrl) & DEVCTRL_HS) { |
| 334 | puts("fotg210: HS\n"); |
| 335 | chip->gadget.speed = USB_SPEED_HIGH; |
| 336 | /* SOF mask timer = 1100 ticks */ |
| 337 | writel(SOFMTR_TMR(1100), ®s->sof_mtr); |
| 338 | } else { |
| 339 | puts("fotg210: FS\n"); |
| 340 | chip->gadget.speed = USB_SPEED_FULL; |
| 341 | /* SOF mask timer = 10000 ticks */ |
| 342 | writel(SOFMTR_TMR(10000), ®s->sof_mtr); |
| 343 | } |
| 344 | } else { |
| 345 | printf("fotg210: mini-A?\n"); |
| 346 | } |
| 347 | } |
| 348 | |
| 349 | /* switch data port to ep0 */ |
| 350 | writel(DMAFIFO_CX, ®s->dma_fifo); |
| 351 | /* fetch 8 bytes setup packet */ |
| 352 | tmp[0] = readl(®s->ep0_data); |
| 353 | tmp[1] = readl(®s->ep0_data); |
| 354 | /* release data port */ |
| 355 | writel(0, ®s->dma_fifo); |
| 356 | |
| 357 | if (req->bRequestType & USB_DIR_IN) |
| 358 | ep0_desc.bEndpointAddress = USB_DIR_IN; |
| 359 | else |
| 360 | ep0_desc.bEndpointAddress = USB_DIR_OUT; |
| 361 | |
| 362 | ret = CX_IDLE; |
| 363 | |
| 364 | if ((req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { |
| 365 | switch (req->bRequest) { |
| 366 | case USB_REQ_SET_CONFIGURATION: |
| 367 | debug("fotg210: set_cfg(%d)\n", req->wValue & 0x00FF); |
| 368 | if (!(req->wValue & 0x00FF)) { |
| 369 | chip->state = USB_STATE_ADDRESS; |
| 370 | writel(chip->addr, ®s->dev_addr); |
| 371 | } else { |
| 372 | chip->state = USB_STATE_CONFIGURED; |
| 373 | writel(chip->addr | DEVADDR_CONF, |
| 374 | ®s->dev_addr); |
| 375 | } |
| 376 | ret = CX_IDLE; |
| 377 | break; |
| 378 | |
| 379 | case USB_REQ_SET_ADDRESS: |
| 380 | debug("fotg210: set_addr(0x%04X)\n", req->wValue); |
| 381 | chip->state = USB_STATE_ADDRESS; |
| 382 | chip->addr = req->wValue & DEVADDR_ADDR_MASK; |
| 383 | ret = CX_FINISH; |
| 384 | writel(chip->addr, ®s->dev_addr); |
| 385 | break; |
| 386 | |
| 387 | case USB_REQ_CLEAR_FEATURE: |
| 388 | debug("fotg210: clr_feature(%d, %d)\n", |
| 389 | req->bRequestType & 0x03, req->wValue); |
| 390 | switch (req->wValue) { |
| 391 | case 0: /* [Endpoint] halt */ |
| 392 | ep_reset(chip, req->wIndex); |
| 393 | ret = CX_FINISH; |
| 394 | break; |
| 395 | case 1: /* [Device] remote wake-up */ |
| 396 | case 2: /* [Device] test mode */ |
| 397 | default: |
| 398 | ret = CX_STALL; |
| 399 | break; |
| 400 | } |
| 401 | break; |
| 402 | |
| 403 | case USB_REQ_SET_FEATURE: |
| 404 | debug("fotg210: set_feature(%d, %d)\n", |
| 405 | req->wValue, req->wIndex & 0xf); |
| 406 | switch (req->wValue) { |
| 407 | case 0: /* Endpoint Halt */ |
| 408 | id = req->wIndex & 0xf; |
| 409 | setbits_le32(®s->iep[id - 1], IEP_STALL); |
| 410 | setbits_le32(®s->oep[id - 1], OEP_STALL); |
| 411 | ret = CX_FINISH; |
| 412 | break; |
| 413 | case 1: /* Remote Wakeup */ |
| 414 | case 2: /* Test Mode */ |
| 415 | default: |
| 416 | ret = CX_STALL; |
| 417 | break; |
| 418 | } |
| 419 | break; |
| 420 | |
| 421 | case USB_REQ_GET_STATUS: |
| 422 | debug("fotg210: get_status\n"); |
| 423 | ret = CX_STALL; |
| 424 | break; |
| 425 | |
| 426 | case USB_REQ_SET_DESCRIPTOR: |
| 427 | debug("fotg210: set_descriptor\n"); |
| 428 | ret = CX_STALL; |
| 429 | break; |
| 430 | |
| 431 | case USB_REQ_SYNCH_FRAME: |
| 432 | debug("fotg210: sync frame\n"); |
| 433 | ret = CX_STALL; |
| 434 | break; |
| 435 | } |
| 436 | } /* if ((req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) */ |
| 437 | |
| 438 | if (ret == CX_IDLE && chip->driver->setup) { |
| 439 | if (chip->driver->setup(&chip->gadget, req) < 0) |
| 440 | ret = CX_STALL; |
| 441 | else |
| 442 | ret = CX_FINISH; |
| 443 | } |
| 444 | |
| 445 | switch (ret) { |
| 446 | case CX_FINISH: |
| 447 | setbits_le32(®s->cxfifo, CXFIFO_CXFIN); |
| 448 | break; |
| 449 | |
| 450 | case CX_STALL: |
| 451 | setbits_le32(®s->cxfifo, CXFIFO_CXSTALL | CXFIFO_CXFIN); |
| 452 | printf("fotg210: cx_stall!\n"); |
| 453 | break; |
| 454 | |
| 455 | case CX_IDLE: |
| 456 | debug("fotg210: cx_idle?\n"); |
| 457 | default: |
| 458 | break; |
| 459 | } |
| 460 | } |
| 461 | |
| 462 | /* |
| 463 | * fifo - FIFO id |
| 464 | * zlp - zero length packet |
| 465 | */ |
| 466 | static void fotg210_recv(struct fotg210_chip *chip, int ep_id) |
| 467 | { |
| 468 | struct fotg210_regs *regs = chip->regs; |
| 469 | struct fotg210_ep *ep = chip->ep + ep_id; |
| 470 | struct fotg210_request *req; |
| 471 | int len; |
| 472 | |
| 473 | if (ep->stopped || (ep->desc->bEndpointAddress & USB_DIR_IN)) { |
| 474 | printf("fotg210: ep%d recv, invalid!\n", ep->id); |
| 475 | return; |
| 476 | } |
| 477 | |
| 478 | if (list_empty(&ep->queue)) { |
| 479 | printf("fotg210: ep%d recv, drop!\n", ep->id); |
| 480 | return; |
| 481 | } |
| 482 | |
| 483 | req = list_first_entry(&ep->queue, struct fotg210_request, queue); |
| 484 | len = fotg210_dma(ep, req); |
| 485 | if (len < ep->ep.maxpacket || req->req.length <= req->req.actual) { |
| 486 | list_del_init(&req->queue); |
| 487 | if (req->req.complete) |
| 488 | req->req.complete(&ep->ep, &req->req); |
| 489 | } |
| 490 | |
| 491 | if (ep->id > 0 && list_empty(&ep->queue)) { |
| 492 | setbits_le32(®s->gimr1, |
| 493 | GIMR1_FIFO_RX(ep_to_fifo(chip, ep->id))); |
| 494 | } |
| 495 | } |
| 496 | |
| 497 | /* |
| 498 | * USB Gadget Layer |
| 499 | */ |
| 500 | static int fotg210_ep_enable( |
| 501 | struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc) |
| 502 | { |
| 503 | struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep); |
| 504 | struct fotg210_chip *chip = ep->chip; |
| 505 | struct fotg210_regs *regs = chip->regs; |
| 506 | int id = ep_to_fifo(chip, ep->id); |
| 507 | int in = (desc->bEndpointAddress & USB_DIR_IN) ? 1 : 0; |
| 508 | |
| 509 | if (!_ep || !desc |
| 510 | || desc->bDescriptorType != USB_DT_ENDPOINT |
| 511 | || le16_to_cpu(desc->wMaxPacketSize) == 0) { |
| 512 | printf("fotg210: bad ep or descriptor\n"); |
| 513 | return -EINVAL; |
| 514 | } |
| 515 | |
| 516 | ep->desc = desc; |
| 517 | ep->stopped = 0; |
| 518 | |
| 519 | if (in) |
| 520 | setbits_le32(®s->fifomap, FIFOMAP(id, FIFOMAP_IN)); |
| 521 | |
| 522 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
| 523 | case USB_ENDPOINT_XFER_CONTROL: |
| 524 | return -EINVAL; |
| 525 | |
| 526 | case USB_ENDPOINT_XFER_ISOC: |
| 527 | setbits_le32(®s->fifocfg, |
| 528 | FIFOCFG(id, FIFOCFG_EN | FIFOCFG_ISOC)); |
| 529 | break; |
| 530 | |
| 531 | case USB_ENDPOINT_XFER_BULK: |
| 532 | setbits_le32(®s->fifocfg, |
| 533 | FIFOCFG(id, FIFOCFG_EN | FIFOCFG_BULK)); |
| 534 | break; |
| 535 | |
| 536 | case USB_ENDPOINT_XFER_INT: |
| 537 | setbits_le32(®s->fifocfg, |
| 538 | FIFOCFG(id, FIFOCFG_EN | FIFOCFG_INTR)); |
| 539 | break; |
| 540 | } |
| 541 | |
| 542 | return 0; |
| 543 | } |
| 544 | |
| 545 | static int fotg210_ep_disable(struct usb_ep *_ep) |
| 546 | { |
| 547 | struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep); |
| 548 | struct fotg210_chip *chip = ep->chip; |
| 549 | struct fotg210_regs *regs = chip->regs; |
| 550 | int id = ep_to_fifo(chip, ep->id); |
| 551 | |
| 552 | ep->desc = NULL; |
| 553 | ep->stopped = 1; |
| 554 | |
| 555 | clrbits_le32(®s->fifocfg, FIFOCFG(id, FIFOCFG_CFG_MASK)); |
| 556 | clrbits_le32(®s->fifomap, FIFOMAP(id, FIFOMAP_DIR_MASK)); |
| 557 | |
| 558 | return 0; |
| 559 | } |
| 560 | |
| 561 | static struct usb_request *fotg210_ep_alloc_request( |
| 562 | struct usb_ep *_ep, gfp_t gfp_flags) |
| 563 | { |
| 564 | struct fotg210_request *req = malloc(sizeof(*req)); |
| 565 | |
| 566 | if (req) { |
| 567 | memset(req, 0, sizeof(*req)); |
| 568 | INIT_LIST_HEAD(&req->queue); |
| 569 | } |
| 570 | return &req->req; |
| 571 | } |
| 572 | |
| 573 | static void fotg210_ep_free_request( |
| 574 | struct usb_ep *_ep, struct usb_request *_req) |
| 575 | { |
| 576 | struct fotg210_request *req; |
| 577 | |
| 578 | req = container_of(_req, struct fotg210_request, req); |
| 579 | free(req); |
| 580 | } |
| 581 | |
| 582 | static int fotg210_ep_queue( |
| 583 | struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) |
| 584 | { |
| 585 | struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep); |
| 586 | struct fotg210_chip *chip = ep->chip; |
| 587 | struct fotg210_regs *regs = chip->regs; |
| 588 | struct fotg210_request *req; |
| 589 | |
| 590 | req = container_of(_req, struct fotg210_request, req); |
| 591 | if (!_req || !_req->complete || !_req->buf |
| 592 | || !list_empty(&req->queue)) { |
| 593 | printf("fotg210: invalid request to ep%d\n", ep->id); |
| 594 | return -EINVAL; |
| 595 | } |
| 596 | |
| 597 | if (!chip || chip->state == USB_STATE_SUSPENDED) { |
| 598 | printf("fotg210: request while chip suspended\n"); |
| 599 | return -EINVAL; |
| 600 | } |
| 601 | |
| 602 | req->req.actual = 0; |
| 603 | req->req.status = -EINPROGRESS; |
| 604 | |
| 605 | if (req->req.length == 0) { |
| 606 | req->req.status = 0; |
| 607 | if (req->req.complete) |
| 608 | req->req.complete(&ep->ep, &req->req); |
| 609 | return 0; |
| 610 | } |
| 611 | |
| 612 | if (ep->id == 0) { |
| 613 | do { |
| 614 | int len = fotg210_dma(ep, req); |
| 615 | if (len < ep->ep.maxpacket) |
| 616 | break; |
| 617 | if (ep->desc->bEndpointAddress & USB_DIR_IN) |
| 618 | udelay(100); |
| 619 | } while (req->req.length > req->req.actual); |
| 620 | } else { |
| 621 | if (ep->desc->bEndpointAddress & USB_DIR_IN) { |
| 622 | do { |
| 623 | int len = fotg210_dma(ep, req); |
| 624 | if (len < ep->ep.maxpacket) |
| 625 | break; |
| 626 | } while (req->req.length > req->req.actual); |
| 627 | } else { |
| 628 | list_add_tail(&req->queue, &ep->queue); |
| 629 | clrbits_le32(®s->gimr1, |
| 630 | GIMR1_FIFO_RX(ep_to_fifo(chip, ep->id))); |
| 631 | } |
| 632 | } |
| 633 | |
| 634 | if (ep->id == 0 || (ep->desc->bEndpointAddress & USB_DIR_IN)) { |
| 635 | if (req->req.complete) |
| 636 | req->req.complete(&ep->ep, &req->req); |
| 637 | } |
| 638 | |
| 639 | return 0; |
| 640 | } |
| 641 | |
| 642 | static int fotg210_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) |
| 643 | { |
| 644 | struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep); |
| 645 | struct fotg210_request *req; |
| 646 | |
| 647 | /* make sure it's actually queued on this endpoint */ |
| 648 | list_for_each_entry(req, &ep->queue, queue) { |
| 649 | if (&req->req == _req) |
| 650 | break; |
| 651 | } |
| 652 | if (&req->req != _req) |
| 653 | return -EINVAL; |
| 654 | |
| 655 | /* remove the request */ |
| 656 | list_del_init(&req->queue); |
| 657 | |
| 658 | /* update status & invoke complete callback */ |
| 659 | if (req->req.status == -EINPROGRESS) { |
| 660 | req->req.status = -ECONNRESET; |
| 661 | if (req->req.complete) |
| 662 | req->req.complete(_ep, &req->req); |
| 663 | } |
| 664 | |
| 665 | return 0; |
| 666 | } |
| 667 | |
| 668 | static int fotg210_ep_halt(struct usb_ep *_ep, int halt) |
| 669 | { |
| 670 | struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep); |
| 671 | struct fotg210_chip *chip = ep->chip; |
| 672 | struct fotg210_regs *regs = chip->regs; |
| 673 | int ret = -1; |
| 674 | |
| 675 | debug("fotg210: ep%d halt=%d\n", ep->id, halt); |
| 676 | |
| 677 | /* Endpoint STALL */ |
| 678 | if (ep->id > 0 && ep->id <= CFG_NUM_ENDPOINTS) { |
| 679 | if (halt) { |
| 680 | /* wait until all ep fifo empty */ |
| 681 | fotg210_cxwait(chip, 0xf00); |
| 682 | /* stall */ |
| 683 | if (ep->desc->bEndpointAddress & USB_DIR_IN) { |
| 684 | setbits_le32(®s->iep[ep->id - 1], |
| 685 | IEP_STALL); |
| 686 | } else { |
| 687 | setbits_le32(®s->oep[ep->id - 1], |
| 688 | OEP_STALL); |
| 689 | } |
| 690 | } else { |
| 691 | if (ep->desc->bEndpointAddress & USB_DIR_IN) { |
| 692 | clrbits_le32(®s->iep[ep->id - 1], |
| 693 | IEP_STALL); |
| 694 | } else { |
| 695 | clrbits_le32(®s->oep[ep->id - 1], |
| 696 | OEP_STALL); |
| 697 | } |
| 698 | } |
| 699 | ret = 0; |
| 700 | } |
| 701 | |
| 702 | return ret; |
| 703 | } |
| 704 | |
| 705 | /* |
| 706 | * activate/deactivate link with host. |
| 707 | */ |
| 708 | static void pullup(struct fotg210_chip *chip, int is_on) |
| 709 | { |
| 710 | struct fotg210_regs *regs = chip->regs; |
| 711 | |
| 712 | if (is_on) { |
| 713 | if (!chip->pullup) { |
| 714 | chip->state = USB_STATE_POWERED; |
| 715 | chip->pullup = 1; |
| 716 | /* enable the chip */ |
| 717 | setbits_le32(®s->dev_ctrl, DEVCTRL_EN); |
| 718 | /* clear unplug bit (BIT0) */ |
| 719 | clrbits_le32(®s->phy_tmsr, PHYTMSR_UNPLUG); |
| 720 | } |
| 721 | } else { |
| 722 | chip->state = USB_STATE_NOTATTACHED; |
| 723 | chip->pullup = 0; |
| 724 | chip->addr = 0; |
| 725 | writel(chip->addr, ®s->dev_addr); |
| 726 | /* set unplug bit (BIT0) */ |
| 727 | setbits_le32(®s->phy_tmsr, PHYTMSR_UNPLUG); |
| 728 | /* disable the chip */ |
| 729 | clrbits_le32(®s->dev_ctrl, DEVCTRL_EN); |
| 730 | } |
| 731 | } |
| 732 | |
| 733 | static int fotg210_pullup(struct usb_gadget *_gadget, int is_on) |
| 734 | { |
| 735 | struct fotg210_chip *chip; |
| 736 | |
| 737 | chip = container_of(_gadget, struct fotg210_chip, gadget); |
| 738 | |
| 739 | debug("fotg210: pullup=%d\n", is_on); |
| 740 | |
| 741 | pullup(chip, is_on); |
| 742 | |
| 743 | return 0; |
| 744 | } |
| 745 | |
| 746 | static int fotg210_get_frame(struct usb_gadget *_gadget) |
| 747 | { |
| 748 | struct fotg210_chip *chip; |
| 749 | struct fotg210_regs *regs; |
| 750 | |
| 751 | chip = container_of(_gadget, struct fotg210_chip, gadget); |
| 752 | regs = chip->regs; |
| 753 | |
| 754 | return SOFFNR_FNR(readl(®s->sof_fnr)); |
| 755 | } |
| 756 | |
| 757 | static struct usb_gadget_ops fotg210_gadget_ops = { |
| 758 | .get_frame = fotg210_get_frame, |
| 759 | .pullup = fotg210_pullup, |
| 760 | }; |
| 761 | |
| 762 | static struct usb_ep_ops fotg210_ep_ops = { |
| 763 | .enable = fotg210_ep_enable, |
| 764 | .disable = fotg210_ep_disable, |
| 765 | .queue = fotg210_ep_queue, |
| 766 | .dequeue = fotg210_ep_dequeue, |
| 767 | .set_halt = fotg210_ep_halt, |
| 768 | .alloc_request = fotg210_ep_alloc_request, |
| 769 | .free_request = fotg210_ep_free_request, |
| 770 | }; |
| 771 | |
| 772 | static struct fotg210_chip controller = { |
| 773 | .regs = (void __iomem *)CONFIG_FOTG210_BASE, |
| 774 | .gadget = { |
| 775 | .name = "fotg210_udc", |
| 776 | .ops = &fotg210_gadget_ops, |
| 777 | .ep0 = &controller.ep[0].ep, |
| 778 | .speed = USB_SPEED_UNKNOWN, |
| 779 | .is_dualspeed = 1, |
| 780 | .is_otg = 0, |
| 781 | .is_a_peripheral = 0, |
| 782 | .b_hnp_enable = 0, |
| 783 | .a_hnp_support = 0, |
| 784 | .a_alt_hnp_support = 0, |
| 785 | }, |
| 786 | .ep[0] = { |
| 787 | .id = 0, |
| 788 | .ep = { |
| 789 | .name = "ep0", |
| 790 | .ops = &fotg210_ep_ops, |
| 791 | }, |
| 792 | .desc = &ep0_desc, |
| 793 | .chip = &controller, |
| 794 | .maxpacket = CFG_EP0_MAX_PACKET_SIZE, |
| 795 | }, |
| 796 | .ep[1] = { |
| 797 | .id = 1, |
| 798 | .ep = { |
| 799 | .name = "ep1", |
| 800 | .ops = &fotg210_ep_ops, |
| 801 | }, |
| 802 | .chip = &controller, |
| 803 | .maxpacket = CFG_EPX_MAX_PACKET_SIZE, |
| 804 | }, |
| 805 | .ep[2] = { |
| 806 | .id = 2, |
| 807 | .ep = { |
| 808 | .name = "ep2", |
| 809 | .ops = &fotg210_ep_ops, |
| 810 | }, |
| 811 | .chip = &controller, |
| 812 | .maxpacket = CFG_EPX_MAX_PACKET_SIZE, |
| 813 | }, |
| 814 | .ep[3] = { |
| 815 | .id = 3, |
| 816 | .ep = { |
| 817 | .name = "ep3", |
| 818 | .ops = &fotg210_ep_ops, |
| 819 | }, |
| 820 | .chip = &controller, |
| 821 | .maxpacket = CFG_EPX_MAX_PACKET_SIZE, |
| 822 | }, |
| 823 | .ep[4] = { |
| 824 | .id = 4, |
| 825 | .ep = { |
| 826 | .name = "ep4", |
| 827 | .ops = &fotg210_ep_ops, |
| 828 | }, |
| 829 | .chip = &controller, |
| 830 | .maxpacket = CFG_EPX_MAX_PACKET_SIZE, |
| 831 | }, |
| 832 | }; |
| 833 | |
| 834 | int usb_gadget_handle_interrupts(void) |
| 835 | { |
| 836 | struct fotg210_chip *chip = &controller; |
| 837 | struct fotg210_regs *regs = chip->regs; |
| 838 | uint32_t id, st, isr, gisr; |
| 839 | |
| 840 | isr = readl(®s->isr) & (~readl(®s->imr)); |
| 841 | gisr = readl(®s->gisr) & (~readl(®s->gimr)); |
| 842 | if (!(isr & ISR_DEV) || !gisr) |
| 843 | return 0; |
| 844 | |
| 845 | writel(ISR_DEV, ®s->isr); |
| 846 | |
| 847 | /* CX interrupts */ |
| 848 | if (gisr & GISR_GRP0) { |
| 849 | st = readl(®s->gisr0); |
Kuo-Jung Su | e8acd19 | 2013-12-20 12:32:59 +0800 | [diff] [blame^] | 850 | /* |
| 851 | * Write 1 and then 0 works for both W1C & RW. |
| 852 | * |
| 853 | * HW v1.11.0+: It's a W1C register (write 1 clear) |
| 854 | * HW v1.10.0-: It's a R/W register (write 0 clear) |
| 855 | */ |
| 856 | writel(st & GISR0_CXABORT, ®s->gisr0); |
Kuo-Jung Su | 78ba07d | 2013-05-15 15:29:24 +0800 | [diff] [blame] | 857 | writel(0, ®s->gisr0); |
| 858 | |
| 859 | if (st & GISR0_CXERR) |
| 860 | printf("fotg210: cmd error\n"); |
| 861 | |
| 862 | if (st & GISR0_CXABORT) |
| 863 | printf("fotg210: cmd abort\n"); |
| 864 | |
| 865 | if (st & GISR0_CXSETUP) /* setup */ |
| 866 | fotg210_setup(chip); |
| 867 | else if (st & GISR0_CXEND) /* command finish */ |
| 868 | setbits_le32(®s->cxfifo, CXFIFO_CXFIN); |
| 869 | } |
| 870 | |
| 871 | /* FIFO interrupts */ |
| 872 | if (gisr & GISR_GRP1) { |
| 873 | st = readl(®s->gisr1); |
| 874 | for (id = 0; id < 4; ++id) { |
| 875 | if (st & GISR1_RX_FIFO(id)) |
| 876 | fotg210_recv(chip, fifo_to_ep(chip, id, 0)); |
| 877 | } |
| 878 | } |
| 879 | |
| 880 | /* Device Status Interrupts */ |
| 881 | if (gisr & GISR_GRP2) { |
| 882 | st = readl(®s->gisr2); |
Kuo-Jung Su | e8acd19 | 2013-12-20 12:32:59 +0800 | [diff] [blame^] | 883 | /* |
| 884 | * Write 1 and then 0 works for both W1C & RW. |
| 885 | * |
| 886 | * HW v1.11.0+: It's a W1C register (write 1 clear) |
| 887 | * HW v1.10.0-: It's a R/W register (write 0 clear) |
| 888 | */ |
| 889 | writel(st, ®s->gisr2); |
Kuo-Jung Su | 78ba07d | 2013-05-15 15:29:24 +0800 | [diff] [blame] | 890 | writel(0, ®s->gisr2); |
| 891 | |
| 892 | if (st & GISR2_RESET) |
| 893 | printf("fotg210: reset by host\n"); |
| 894 | else if (st & GISR2_SUSPEND) |
| 895 | printf("fotg210: suspend/removed\n"); |
| 896 | else if (st & GISR2_RESUME) |
| 897 | printf("fotg210: resume\n"); |
| 898 | |
| 899 | /* Errors */ |
| 900 | if (st & GISR2_ISOCERR) |
| 901 | printf("fotg210: iso error\n"); |
| 902 | if (st & GISR2_ISOCABT) |
| 903 | printf("fotg210: iso abort\n"); |
| 904 | if (st & GISR2_DMAERR) |
| 905 | printf("fotg210: dma error\n"); |
| 906 | } |
| 907 | |
| 908 | return 0; |
| 909 | } |
| 910 | |
| 911 | int usb_gadget_register_driver(struct usb_gadget_driver *driver) |
| 912 | { |
| 913 | int i, ret = 0; |
| 914 | struct fotg210_chip *chip = &controller; |
| 915 | |
| 916 | if (!driver || !driver->bind || !driver->setup) { |
| 917 | puts("fotg210: bad parameter.\n"); |
| 918 | return -EINVAL; |
| 919 | } |
| 920 | |
| 921 | INIT_LIST_HEAD(&chip->gadget.ep_list); |
| 922 | for (i = 0; i < CFG_NUM_ENDPOINTS + 1; ++i) { |
| 923 | struct fotg210_ep *ep = chip->ep + i; |
| 924 | |
| 925 | ep->ep.maxpacket = ep->maxpacket; |
| 926 | INIT_LIST_HEAD(&ep->queue); |
| 927 | |
| 928 | if (ep->id == 0) { |
| 929 | ep->stopped = 0; |
| 930 | } else { |
| 931 | ep->stopped = 1; |
| 932 | list_add_tail(&ep->ep.ep_list, &chip->gadget.ep_list); |
| 933 | } |
| 934 | } |
| 935 | |
| 936 | if (fotg210_reset(chip)) { |
| 937 | puts("fotg210: reset failed.\n"); |
| 938 | return -EINVAL; |
| 939 | } |
| 940 | |
| 941 | ret = driver->bind(&chip->gadget); |
| 942 | if (ret) { |
| 943 | debug("fotg210: driver->bind() returned %d\n", ret); |
| 944 | return ret; |
| 945 | } |
| 946 | chip->driver = driver; |
| 947 | |
| 948 | return ret; |
| 949 | } |
| 950 | |
| 951 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) |
| 952 | { |
| 953 | struct fotg210_chip *chip = &controller; |
| 954 | |
| 955 | driver->unbind(&chip->gadget); |
| 956 | chip->driver = NULL; |
| 957 | |
| 958 | pullup(chip, 0); |
| 959 | |
| 960 | return 0; |
| 961 | } |