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wdenk9b7f3842003-10-09 20:09:04 +00001/*
2 * (C) Copyright 2003
3 * Thomas.Lange@corelatus.se
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk9b7f3842003-10-09 20:09:04 +00006 */
7
8#include <common.h>
9#include <command.h>
Daniel Schwierzeck536ce922015-12-21 16:35:14 +010010#include <mach/au1x00.h>
wdenk9b7f3842003-10-09 20:09:04 +000011#include <asm/mipsregs.h>
Jean-Christophe PLAGNIOL-VILLARD089dbb72007-11-13 09:11:05 +010012#include <asm/io.h>
wdenk9b7f3842003-10-09 20:09:04 +000013
Becky Brucebd99ae72008-06-09 16:03:40 -050014phys_size_t initdram(int board_type)
wdenk9b7f3842003-10-09 20:09:04 +000015{
16 /* Sdram is setup by assembler code */
17 /* If memory could be changed, we should return the true value here */
wdenk96c7a8c2005-01-09 22:28:56 +000018 return MEM_SIZE*1024*1024;
wdenk9b7f3842003-10-09 20:09:04 +000019}
20
21#define BCSR_PCMCIA_PC0DRVEN 0x0010
22#define BCSR_PCMCIA_PC0RST 0x0080
23
Peter Tyser1d85dee2010-04-12 22:28:14 -050024/* In arch/mips/cpu/cpu.c */
wdenk9b7f3842003-10-09 20:09:04 +000025void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
26
27int checkboard (void)
28{
wdenk525d7b62005-01-22 18:13:04 +000029#ifdef CONFIG_IDE_PCMCIA
wdenk9b7f3842003-10-09 20:09:04 +000030 u16 status;
wdenk96c7a8c2005-01-09 22:28:56 +000031 volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10);
wdenk525d7b62005-01-22 18:13:04 +000032#endif /* CONFIG_IDE_PCMCIA */
wdenk96c7a8c2005-01-09 22:28:56 +000033 volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC);
wdenk9b7f3842003-10-09 20:09:04 +000034 volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
35 u32 proc_id;
36
37 *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
38
Shinya Kuribayashi0fdd27e2008-05-30 00:53:38 +090039 proc_id = read_c0_prid();
wdenk9b7f3842003-10-09 20:09:04 +000040
wdenk4ea537d2003-12-07 18:32:37 +000041 switch (proc_id >> 24) {
wdenk9b7f3842003-10-09 20:09:04 +000042 case 0:
wdenk4ea537d2003-12-07 18:32:37 +000043 puts ("Board: Merlot (DbAu1000)\n");
44 printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
45 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
46 break;
47 case 1:
48 puts ("Board: DbAu1500\n");
49 printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
50 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
51 break;
52 case 2:
53 puts ("Board: DbAu1100\n");
54 printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
55 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
56 break;
wdenk96c7a8c2005-01-09 22:28:56 +000057 case 3:
58 puts ("Board: DbAu1550\n");
59 printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
60 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
61 break;
wdenk9b7f3842003-10-09 20:09:04 +000062 default:
wdenk4ea537d2003-12-07 18:32:37 +000063 printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
wdenk9b7f3842003-10-09 20:09:04 +000064 }
Jean-Christophe PLAGNIOL-VILLARD089dbb72007-11-13 09:11:05 +010065
66 set_io_port_base(0);
67
wdenk9b7f3842003-10-09 20:09:04 +000068#ifdef CONFIG_IDE_PCMCIA
69 /* Enable 3.3 V on slot 0 ( VCC )
70 No 5V */
71 status = 4;
72 *pcmcia_bcsr = status;
73
74 status |= BCSR_PCMCIA_PC0DRVEN;
75 *pcmcia_bcsr = status;
76 au_sync();
77
78 udelay(300*1000);
79
80 status |= BCSR_PCMCIA_PC0RST;
81 *pcmcia_bcsr = status;
82 au_sync();
83
84 udelay(100*1000);
85
86 /* PCMCIA is on a 36 bit physical address.
87 We need to map it into a 32 bit addresses */
88
89#if 0
90 /* We dont need theese unless we run whole pcmcia package */
91 write_one_tlb(20, /* index */
92 0x01ffe000, /* Pagemask, 16 MB pages */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020093 CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
wdenk9b7f3842003-10-09 20:09:04 +000094 0x3C000017, /* Lo0 */
95 0x3C200017); /* Lo1 */
96
97 write_one_tlb(21, /* index */
98 0x01ffe000, /* Pagemask, 16 MB pages */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099 CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
wdenk9b7f3842003-10-09 20:09:04 +0000100 0x3D000017, /* Lo0 */
101 0x3D200017); /* Lo1 */
wdenk604b7a12004-06-09 15:29:49 +0000102#endif /* 0 */
wdenk9b7f3842003-10-09 20:09:04 +0000103 write_one_tlb(22, /* index */
104 0x01ffe000, /* Pagemask, 16 MB pages */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200105 CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
wdenk9b7f3842003-10-09 20:09:04 +0000106 0x3E000017, /* Lo0 */
107 0x3E200017); /* Lo1 */
wdenk604b7a12004-06-09 15:29:49 +0000108#endif /* CONFIG_IDE_PCMCIA */
wdenk9b7f3842003-10-09 20:09:04 +0000109
110 /* Release reset of ethernet PHY chips */
111 /* Always do this, because linux does not know about it */
112 *phy = 3;
113
114 return 0;
wdenk9b7f3842003-10-09 20:09:04 +0000115}