Anup Patel | 8d28c3c | 2019-02-25 08:14:55 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (c) 2019 Western Digital Corporation or its affiliates. |
| 4 | * |
| 5 | * Author: Anup Patel <anup.patel@wdc.com> |
| 6 | */ |
| 7 | |
Patrick Delaunay | 8767e79 | 2021-11-19 15:12:07 +0100 | [diff] [blame] | 8 | #define LOG_CATEGORY UCLASS_CLK |
| 9 | |
Anup Patel | 8d28c3c | 2019-02-25 08:14:55 +0000 | [diff] [blame] | 10 | #include <common.h> |
| 11 | #include <clk-uclass.h> |
| 12 | #include <div64.h> |
| 13 | #include <dm.h> |
Patrick Delaunay | 8767e79 | 2021-11-19 15:12:07 +0100 | [diff] [blame] | 14 | #include <log.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 15 | #include <linux/err.h> |
Anup Patel | 8d28c3c | 2019-02-25 08:14:55 +0000 | [diff] [blame] | 16 | |
| 17 | struct clk_fixed_factor { |
| 18 | struct clk parent; |
| 19 | unsigned int div; |
| 20 | unsigned int mult; |
| 21 | }; |
| 22 | |
| 23 | #define to_clk_fixed_factor(dev) \ |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 24 | ((struct clk_fixed_factor *)dev_get_plat(dev)) |
Anup Patel | 8d28c3c | 2019-02-25 08:14:55 +0000 | [diff] [blame] | 25 | |
| 26 | static ulong clk_fixed_factor_get_rate(struct clk *clk) |
| 27 | { |
| 28 | uint64_t rate; |
| 29 | struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev); |
| 30 | |
Anup Patel | 8d28c3c | 2019-02-25 08:14:55 +0000 | [diff] [blame] | 31 | rate = clk_get_rate(&ff->parent); |
| 32 | if (IS_ERR_VALUE(rate)) |
| 33 | return rate; |
| 34 | |
| 35 | do_div(rate, ff->div); |
| 36 | |
| 37 | return rate * ff->mult; |
| 38 | } |
| 39 | |
| 40 | const struct clk_ops clk_fixed_factor_ops = { |
| 41 | .get_rate = clk_fixed_factor_get_rate, |
| 42 | }; |
| 43 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 44 | static int clk_fixed_factor_of_to_plat(struct udevice *dev) |
Anup Patel | 8d28c3c | 2019-02-25 08:14:55 +0000 | [diff] [blame] | 45 | { |
Simon Glass | 6d70ba0 | 2021-08-07 07:24:06 -0600 | [diff] [blame] | 46 | if (CONFIG_IS_ENABLED(OF_REAL)) { |
| 47 | int err; |
| 48 | struct clk_fixed_factor *ff = to_clk_fixed_factor(dev); |
Anup Patel | 8d28c3c | 2019-02-25 08:14:55 +0000 | [diff] [blame] | 49 | |
Simon Glass | 6d70ba0 | 2021-08-07 07:24:06 -0600 | [diff] [blame] | 50 | err = clk_get_by_index(dev, 0, &ff->parent); |
| 51 | if (err) |
| 52 | return err; |
Anup Patel | 8d28c3c | 2019-02-25 08:14:55 +0000 | [diff] [blame] | 53 | |
Simon Glass | 6d70ba0 | 2021-08-07 07:24:06 -0600 | [diff] [blame] | 54 | ff->div = dev_read_u32_default(dev, "clock-div", 1); |
| 55 | ff->mult = dev_read_u32_default(dev, "clock-mult", 1); |
| 56 | } |
Anup Patel | 8d28c3c | 2019-02-25 08:14:55 +0000 | [diff] [blame] | 57 | |
| 58 | return 0; |
| 59 | } |
| 60 | |
| 61 | static const struct udevice_id clk_fixed_factor_match[] = { |
| 62 | { |
| 63 | .compatible = "fixed-factor-clock", |
| 64 | }, |
| 65 | { /* sentinel */ } |
| 66 | }; |
| 67 | |
| 68 | U_BOOT_DRIVER(clk_fixed_factor) = { |
| 69 | .name = "fixed_factor_clock", |
| 70 | .id = UCLASS_CLK, |
| 71 | .of_match = clk_fixed_factor_match, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 72 | .of_to_plat = clk_fixed_factor_of_to_plat, |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 73 | .plat_auto = sizeof(struct clk_fixed_factor), |
Anup Patel | 8d28c3c | 2019-02-25 08:14:55 +0000 | [diff] [blame] | 74 | .ops = &clk_fixed_factor_ops, |
| 75 | }; |