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git01.mediatek.com / filogic / uboot / e6ce78cf1dfa210a5c874a5c01162de8886de412 / . / include / configs / db-88f6820-gp.h
blob: 3900cbed2d70b1f9a44bfe0430f73df80d7c7363 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]2/*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]4 */
5
6#ifndef _CONFIG_DB_88F6820_GP_H
7#define _CONFIG_DB_88F6820_GP_H
8
9/*
10 * High Level Configuration Options (easy to change)
11 */
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]12
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]13#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
14
15/*
16 * Commands configuration
17 */
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]18
19/* I2C */
20#define CONFIG_SYS_I2C
21#define CONFIG_SYS_I2C_MVTWSI
22#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
23#define CONFIG_SYS_I2C_SLAVE 0x0
24#define CONFIG_SYS_I2C_SPEED 100000
25
Konstantin Porotchkinc6cb8b72018-08-29 16:34:53 +0300[diff] [blame]26/*
27 * SPI Flash configuration for the environemnt access
28 */
29#define CONFIG_ENV_SPI_BUS 0
30#define CONFIG_ENV_SPI_CS 0
31
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]32/* SPI NOR flash default params, used by sf commands */
33#define CONFIG_SF_DEFAULT_SPEED 1000000
34#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]35
Stefan Roese1746e872015-06-29 14:58:11 +0200[diff] [blame]36/*
37 * SDIO/MMC Card Configuration
38 */
Stefan Roese1746e872015-06-29 14:58:11 +0200[diff] [blame]39#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
40
Stefan Roese10aad202015-06-29 14:58:14 +0200[diff] [blame]41/*
42 * SATA/SCSI/AHCI configuration
43 */
Stefan Roese10aad202015-06-29 14:58:14 +0200[diff] [blame]44#define CONFIG_SCSI_AHCI_PLAT
45#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
46#define CONFIG_SYS_SCSI_MAX_LUN 1
47#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
48 CONFIG_SYS_SCSI_MAX_LUN)
49
Stefan Roese2feb2262015-06-29 14:58:16 +0200[diff] [blame]50/* USB/EHCI configuration */
Stefan Roese2feb2262015-06-29 14:58:16 +0200[diff] [blame]51#define CONFIG_EHCI_IS_TDI
52
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]53/* Environment in SPI NOR flash */
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]54#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
55#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
56#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
57
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]58#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
59
Stefan Roesec22b7012015-08-11 12:50:58 +0200[diff] [blame]60/* PCIe support */
Stefan Roese83097cf2015-11-25 07:37:00 +0100[diff] [blame]61#ifndef CONFIG_SPL_BUILD
Stefan Roesec22b7012015-08-11 12:50:58 +0200[diff] [blame]62#define CONFIG_PCI_MVEBU
Stefan Roesec22b7012015-08-11 12:50:58 +0200[diff] [blame]63#define CONFIG_PCI_SCAN_SHOW
Stefan Roese83097cf2015-11-25 07:37:00 +0100[diff] [blame]64#endif
Stefan Roesec22b7012015-08-11 12:50:58 +0200[diff] [blame]65
Kevin Smith2366bcc2015-05-18 16:09:46 +0000[diff] [blame]66/* Keep device tree and initrd in lower memory so the kernel can access them */
67#define CONFIG_EXTRA_ENV_SETTINGS \
68 "fdt_high=0x10000000\0" \
69 "initrd_high=0x10000000\0"
70
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]71/* SPL */
Stefan Roese6f7d6672015-07-20 11:20:40 +0200[diff] [blame]72/*
73 * Select the boot device here
74 *
75 * Currently supported are:
76 * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
77 * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
78 */
79#define SPL_BOOT_SPI_NOR_FLASH 1
80#define SPL_BOOT_SDIO_MMC_CARD 2
81#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
82
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]83/* Defines for SPL */
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]84#define CONFIG_SPL_SIZE (140 << 10)
85#define CONFIG_SPL_TEXT_BASE 0x40000030
86#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
87
88#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
89#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
90
Stefan Roese83097cf2015-11-25 07:37:00 +0100[diff] [blame]91#ifdef CONFIG_SPL_BUILD
92#define CONFIG_SYS_MALLOC_SIMPLE
93#endif
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]94
95#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
96#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
97
Stefan Roese6f7d6672015-07-20 11:20:40 +0200[diff] [blame]98#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]99/* SPL related SPI defines */
Stefan Roese49e7d772015-11-20 13:51:57 +0100[diff] [blame]100#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
Stefan Roese6f7d6672015-07-20 11:20:40 +0200[diff] [blame]101#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
102#endif
103
104#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
105/* SPL related MMC defines */
Stefan Roese6f7d6672015-07-20 11:20:40 +0200[diff] [blame]106#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
107#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
Stefan Roese6f7d6672015-07-20 11:20:40 +0200[diff] [blame]108#ifdef CONFIG_SPL_BUILD
109#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
110#endif
111#endif
Stefan Roese5caab192015-03-25 13:35:15 +0100[diff] [blame]112
Stefan Roese073efd72015-04-25 06:29:56 +0200[diff] [blame]113/*
114 * mv-common.h should be defined after CMD configs since it used them
115 * to enable certain macros
116 */
117#include "mv-common.h"
118
119#endif /* _CONFIG_DB_88F6820_GP_H */