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git01.mediatek.com / filogic / uboot / e6bda8c0716b3d2e17a0e91b1c1f642fbeb62712 / . / arch / arm / mach-exynos / clock_init.h
blob: fce502f45a3671f4d7f105500287bf2e5b1bdff4 [file] [log] [blame]
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]1/*
2 * Clock initialization routines
3 *
4 * Copyright (c) 2011 The Chromium OS Authors.
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]6 * SPDX-License-Identifier: GPL-2.0+
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]7 */
8
9#ifndef __EXYNOS_CLOCK_INIT_H
10#define __EXYNOS_CLOCK_INIT_H
11
12enum {
Rajeshwari Birjeac892d02013-12-26 09:44:21 +0530[diff] [blame]13#ifdef CONFIG_EXYNOS5420
14 MEM_TIMINGS_MSR_COUNT = 5,
15#else
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]16 MEM_TIMINGS_MSR_COUNT = 4,
Rajeshwari Birjeac892d02013-12-26 09:44:21 +0530[diff] [blame]17#endif
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]18};
19
20/* These are the ratio's for configuring ARM clock */
21struct arm_clk_ratios {
22 unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */
23
24 unsigned apll_mdiv;
25 unsigned apll_pdiv;
26 unsigned apll_sdiv;
27
28 unsigned arm2_ratio;
29 unsigned apll_ratio;
30 unsigned pclk_dbg_ratio;
31 unsigned atb_ratio;
32 unsigned periph_ratio;
33 unsigned acp_ratio;
34 unsigned cpud_ratio;
35 unsigned arm_ratio;
36};
37
38/* These are the memory timings for a particular memory type and speed */
39struct mem_timings {
40 enum mem_manuf mem_manuf; /* Memory manufacturer */
41 enum ddr_mode mem_type; /* Memory type */
42 unsigned frequency_mhz; /* Frequency of memory in MHz */
43
44 /* Here follow the timing parameters for the selected memory */
45 unsigned apll_mdiv;
46 unsigned apll_pdiv;
47 unsigned apll_sdiv;
48 unsigned mpll_mdiv;
49 unsigned mpll_pdiv;
50 unsigned mpll_sdiv;
51 unsigned cpll_mdiv;
52 unsigned cpll_pdiv;
53 unsigned cpll_sdiv;
54 unsigned gpll_mdiv;
55 unsigned gpll_pdiv;
56 unsigned gpll_sdiv;
57 unsigned epll_mdiv;
58 unsigned epll_pdiv;
59 unsigned epll_sdiv;
60 unsigned vpll_mdiv;
61 unsigned vpll_pdiv;
62 unsigned vpll_sdiv;
63 unsigned bpll_mdiv;
64 unsigned bpll_pdiv;
65 unsigned bpll_sdiv;
Rajeshwari Birjeac892d02013-12-26 09:44:21 +0530[diff] [blame]66 unsigned kpll_mdiv;
67 unsigned kpll_pdiv;
68 unsigned kpll_sdiv;
69 unsigned dpll_mdiv;
70 unsigned dpll_pdiv;
71 unsigned dpll_sdiv;
72 unsigned ipll_mdiv;
73 unsigned ipll_pdiv;
74 unsigned ipll_sdiv;
75 unsigned spll_mdiv;
76 unsigned spll_pdiv;
77 unsigned spll_sdiv;
Ajay Kumar218eaf32014-09-05 16:53:31 +0530[diff] [blame]78 unsigned rpll_mdiv;
79 unsigned rpll_pdiv;
80 unsigned rpll_sdiv;
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]81 unsigned pclk_cdrex_ratio;
82 unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
83
84 unsigned timing_ref;
85 unsigned timing_row;
86 unsigned timing_data;
87 unsigned timing_power;
88
89 /* DQS, DQ, DEBUG offsets */
90 unsigned phy0_dqs;
91 unsigned phy1_dqs;
92 unsigned phy0_dq;
93 unsigned phy1_dq;
94 unsigned phy0_tFS;
95 unsigned phy1_tFS;
96 unsigned phy0_pulld_dqs;
97 unsigned phy1_pulld_dqs;
98
99 unsigned lpddr3_ctrl_phy_reset;
100 unsigned ctrl_start_point;
101 unsigned ctrl_inc;
102 unsigned ctrl_start;
103 unsigned ctrl_dll_on;
104 unsigned ctrl_ref;
105
106 unsigned ctrl_force;
107 unsigned ctrl_rdlat;
108 unsigned ctrl_bstlen;
109
110 unsigned fp_resync;
111 unsigned iv_size;
112 unsigned dfi_init_start;
113 unsigned aref_en;
114
115 unsigned rd_fetch;
116
117 unsigned zq_mode_dds;
118 unsigned zq_mode_term;
119 unsigned zq_mode_noterm; /* 1 to allow termination disable */
120
121 unsigned memcontrol;
122 unsigned memconfig;
123
124 unsigned membaseconfig0;
125 unsigned membaseconfig1;
126 unsigned prechconfig_tp_cnt;
127 unsigned dpwrdn_cyc;
128 unsigned dsref_cyc;
129 unsigned concontrol;
130 /* Channel and Chip Selection */
131 uint8_t dmc_channels; /* number of memory channels */
132 uint8_t chips_per_channel; /* number of chips per channel */
133 uint8_t chips_to_configure; /* number of chips to configure */
134 uint8_t send_zq_init; /* 1 to send this command */
135 unsigned impedance; /* drive strength impedeance */
136 uint8_t gate_leveling_enable; /* check gate leveling is enabled */
Rajeshwari Birjeac892d02013-12-26 09:44:21 +0530[diff] [blame]137 uint8_t read_leveling_enable; /* check h/w read leveling is enabled */
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]138};
139
140/**
141 * Get the correct memory timings for our selected memory type and speed.
142 *
143 * This function can be called from SPL or the main U-Boot.
144 *
145 * @return pointer to the memory timings that we should use
146 */
147struct mem_timings *clock_get_mem_timings(void);
148
149/*
150 * Initialize clock for the device
151 */
152void system_clock_init(void);
Amare33add82013-04-27 11:42:59 +0530[diff] [blame]153
154/*
155 * Set clock divisor value for booting from EMMC.
156 */
157void emmc_boot_clk_div_set(void);
Rajeshwari Shinde5f90a4c2012-07-03 20:02:55 +0000[diff] [blame]158#endif