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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/*
30 * CPU specific code
31 */
32
33#include <common.h>
34#include <command.h>
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +020035#include <asm/system.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000036
Wolfgang Denk6405a152006-03-31 18:32:53 +020037#ifdef CONFIG_USE_IRQ
38DECLARE_GLOBAL_DATA_PTR;
39#endif
40
wdenk4a9cbbe2002-08-27 09:48:53 +000041int cpu_init (void)
42{
43 /*
wdenkc0aa5c52003-12-06 19:49:23 +000044 * setup up stacks if necessary
wdenk4a9cbbe2002-08-27 09:48:53 +000045 */
46#ifdef CONFIG_USE_IRQ
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020047 IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
wdenkc0aa5c52003-12-06 19:49:23 +000048 FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
wdenk4a9cbbe2002-08-27 09:48:53 +000049#endif
wdenkc0aa5c52003-12-06 19:49:23 +000050 return 0;
wdenk4a9cbbe2002-08-27 09:48:53 +000051}
52
53int cleanup_before_linux (void)
54{
55 /*
56 * this function is called just before we call linux
57 * it prepares the processor for linux
58 *
59 * just disable everything that can disturb booting linux
60 */
61
62 unsigned long i;
63
64 disable_interrupts ();
65
66 /* turn off I-cache */
67 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
68 i &= ~0x1000;
69 asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
70
71 /* flush I-cache */
72 asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
73
74 return (0);
75}
76
77int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
78{
wdenk4a9cbbe2002-08-27 09:48:53 +000079 printf ("resetting ...\n");
80
81 udelay (50000); /* wait 50 ms */
82 disable_interrupts ();
83 reset_cpu (0);
84
85 /*NOTREACHED*/
86 return (0);
87}
88
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +020089static void cp_delay (void)
wdenk4a9cbbe2002-08-27 09:48:53 +000090{
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +020091 volatile int i;
wdenk4a9cbbe2002-08-27 09:48:53 +000092
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +020093 /* copro seems to need some delay between reading and writing */
94 for (i = 0; i < 100; i++);
95}
wdenk4a9cbbe2002-08-27 09:48:53 +000096
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +020097void icache_enable (void)
98{
99 ulong reg;
wdenk4a9cbbe2002-08-27 09:48:53 +0000100
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200101 reg = get_cr ();
102 cp_delay ();
103 set_cr (reg | CR_C);
wdenk4a9cbbe2002-08-27 09:48:53 +0000104}
105
106void icache_disable (void)
107{
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200108 ulong reg;
wdenk4a9cbbe2002-08-27 09:48:53 +0000109
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200110 reg = get_cr ();
111 cp_delay ();
112 set_cr (reg & ~CR_C);
wdenk4a9cbbe2002-08-27 09:48:53 +0000113}
114
115int icache_status (void)
116{
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +0200117 return (get_cr () & CR_C) != 0;
wdenk4a9cbbe2002-08-27 09:48:53 +0000118}
119
120/* we will never enable dcache, because we have to setup MMU first */
121void dcache_enable (void)
122{
123 return;
124}
125
126void dcache_disable (void)
127{
128 return;
129}
130
131int dcache_status (void)
132{
133 return 0; /* always off */
134}