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git01.mediatek.com / filogic / uboot / aa60336798d431e54cd3e554380f1b296139ce63 / . / board / atc / atc.c
blob: 3547f41f93bbeee72ff518d490e0b1a9d7f2e900 [file] [log] [blame]
wdenk541a76d2003-05-03 15:50:43 +0000[diff] [blame]1/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <ioports.h>
26#include <mpc8260.h>
27
28/*
29 * I/O Port configuration table
30 *
31 * if conf is 1, then that port pin will be configured at boot time
32 * according to the five values podr/pdir/ppar/psor/pdat for that entry
33 */
34
35const iop_conf_t iop_conf_tab[4][32] = {
36
37 /* Port A configuration */
38 { /* conf ppar psor pdir podr pdat */
39 /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
40 /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
41 /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
42 /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
43 /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
44 /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
45 /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */
46 /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */
47 /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */
48 /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */
49 /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
50 /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
51 /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
52 /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
53 /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
54 /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
55 /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
56 /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
57 /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */
58 /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */
59 /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */
60 /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */
61#if 1
62 /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
63 /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
64#else
65 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
66 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
67#endif
68 /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
69 /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */
70 /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */
71 /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */
72 /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */
73 /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
74 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */
75 /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */
76 },
77
78 /* Port B configuration */
79 { /* conf ppar psor pdir podr pdat */
80 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
81 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
82 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
83 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
84 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
85 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
86 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
87 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
88 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
89 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
90 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
91 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
92 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
93 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
94 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
95 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
96 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
97 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
98 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
99 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
100 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
101 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
102 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
103 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
104 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
105 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
106 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
107 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
108 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */
109 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */
110 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */
111 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */
112 },
113
114 /* Port C */
115 { /* conf ppar psor pdir podr pdat */
116 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
117 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
118 /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */
119 /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */
120 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
121 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
122 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
123 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
124 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */
125 /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */
126 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
127 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
128 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
129 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
130 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
131 /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
132#if 0
133 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
134#else
135 /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* PC15 */
136#endif
137 /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
138 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
139 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
140 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
141 /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
142 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */
143 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
144 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
145 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
146 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
147 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
148 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
149 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
150 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
151 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */
152 },
153
154 /* Port D */
155 { /* conf ppar psor pdir podr pdat */
156 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
157 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
158 /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */
159 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
160 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */
161 /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */
162 /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
163 /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
164 /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
165 /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
166 /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
167 /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
168 /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
169 /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
170 /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
171 /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
172#if defined(CONFIG_SOFT_I2C)
173 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
174 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
175#else
176#if defined(CONFIG_HARD_I2C)
177 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
178 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
179#else /* normal I/O port pins */
180 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
181 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
182#endif
183#endif
184 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
185 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
186 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
187 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
188 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
189 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
190 /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
191 /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
192 /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
193#if 0
194 /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
195#else
196 /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* PD4 */
197#endif
198 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */
199 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */
200 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */
201 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */
202 }
203};
204
205/* ------------------------------------------------------------------------- */
206
207/* Check Board Identity:
208 */
209int checkboard (void)
210{
211 printf ("Board: ATC\n");
212 return 0;
213}
214
215/* ------------------------------------------------------------------------- */
216
217/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
218 *
219 * This routine performs standard 8260 initialization sequence
220 * and calculates the available memory size. It may be called
221 * several times to try different SDRAM configurations on both
222 * 60x and local buses.
223 */
224static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
225 ulong orx, volatile uchar * base)
226{
227 volatile uchar c = 0xff;
228 ulong cnt, val;
229 volatile ulong *addr;
230 volatile uint *sdmr_ptr;
231 volatile uint *orx_ptr;
232 int i;
233 ulong save[32]; /* to make test non-destructive */
234 ulong maxsize;
235
236 /* We must be able to test a location outsize the maximum legal size
237 * to find out THAT we are outside; but this address still has to be
238 * mapped by the controller. That means, that the initial mapping has
239 * to be (at least) twice as large as the maximum expected size.
240 */
241 maxsize = (1 + (~orx | 0x7fff)) / 2;
242
243 /* Since CFG_SDRAM_BASE is always 0 (??), we assume that
244 * we are configuring CS1 if base != 0
245 */
246 sdmr_ptr = &memctl->memc_psdmr;
247 orx_ptr = &memctl->memc_or2;
248
249 *orx_ptr = orx;
250
251 /*
252 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
253 *
254 * "At system reset, initialization software must set up the
255 * programmable parameters in the memory controller banks registers
256 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
257 * system software should execute the following initialization sequence
258 * for each SDRAM device.
259 *
260 * 1. Issue a PRECHARGE-ALL-BANKS command
261 * 2. Issue eight CBR REFRESH commands
262 * 3. Issue a MODE-SET command to initialize the mode register
263 *
264 * The initial commands are executed by setting P/LSDMR[OP] and
265 * accessing the SDRAM with a single-byte transaction."
266 *
267 * The appropriate BRx/ORx registers have already been set when we
268 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
269 */
270
271 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
272 *base = c;
273
274 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
275 for (i = 0; i < 8; i++)
276 *base = c;
277
278 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
279 *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
280
281 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
282 *base = c;
283
284 /*
285 * Check memory range for valid RAM. A simple memory test determines
286 * the actually available RAM size between addresses `base' and
287 * `base + maxsize'. Some (not all) hardware errors are detected:
288 * - short between address lines
289 * - short between data lines
290 */
291 i = 0;
292 for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
293 addr = (volatile ulong *) base + cnt; /* pointer arith! */
294 save[i++] = *addr;
295 *addr = ~cnt;
296 }
297
298 addr = (volatile ulong *) base;
299 save[i] = *addr;
300 *addr = 0;
301
302 if ((val = *addr) != 0) {
303 *addr = save[i];
304 return (0);
305 }
306
307 for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
308 addr = (volatile ulong *) base + cnt; /* pointer arith! */
309 val = *addr;
310 *addr = save[--i];
311 if (val != ~cnt) {
312 /* Write the actual size to ORx
313 */
314 *orx_ptr = orx | ~(cnt * sizeof (long) - 1);
315 return (cnt * sizeof (long));
316 }
317 }
318 return (maxsize);
319}
320
321long int initdram (int board_type)
322{
323 volatile immap_t *immap = (immap_t *) CFG_IMMR;
324 volatile memctl8260_t *memctl = &immap->im_memctl;
325
326#ifndef CFG_RAMBOOT
327 ulong size8, size9;
328#endif
329 long psize;
330
331 psize = 8 * 1024 * 1024;
332
333 memctl->memc_mptpr = CFG_MPTPR;
334 memctl->memc_psrt = CFG_PSRT;
335
336#ifndef CFG_RAMBOOT
337 /* 60x SDRAM setup:
338 */
339 size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
340 (uchar *) CFG_SDRAM_BASE);
341 size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
342 (uchar *) CFG_SDRAM_BASE);
343
344 if (size8 < size9) {
345 psize = size9;
346 printf ("(60x:9COL) ");
347 } else {
348 psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
349 (uchar *) CFG_SDRAM_BASE);
350 printf ("(60x:8COL) ");
351 }
352
353#endif /* CFG_RAMBOOT */
354
355 icache_enable ();
356
357 return (psize);
358}
359
360#if (CONFIG_COMMANDS & CFG_CMD_DOC)
361extern void doc_probe (ulong physadr);
362void doc_init (void)
363{
364 doc_probe (CFG_DOC_BASE);
365}
366#endif