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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk591dda52002-11-18 00:14:45 +00002/*
Wolfgang Denkf710efd2010-07-24 20:22:02 +02003 * (C) Copyright 2002-2010
wdenk591dda52002-11-18 00:14:45 +00004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenk591dda52002-11-18 00:14:45 +00005 */
6
7#ifndef __ASM_GBL_DATA_H
8#define __ASM_GBL_DATA_H
Simon Glass3ac47d72012-12-13 20:48:30 +00009
10#ifndef __ASSEMBLY__
11
Simon Glass9909bf32015-08-10 20:44:31 -060012#include <asm/processor.h>
Simon Glassc3d0c232019-12-06 21:42:05 -070013#include <asm/mrccache.h>
Simon Glass9909bf32015-08-10 20:44:31 -060014
Simon Glass30580fc2014-11-12 22:42:23 -070015enum pei_boot_mode_t {
16 PEI_BOOT_NONE = 0,
17 PEI_BOOT_SOFT_RESET,
18 PEI_BOOT_RESUME,
19
20};
21
Simon Glassd21f34e2016-03-11 22:07:26 -070022struct dimm_info {
23 uint32_t dimm_size;
24 uint16_t ddr_type;
25 uint16_t ddr_frequency;
26 uint8_t rank_per_dimm;
27 uint8_t channel_num;
28 uint8_t dimm_num;
29 uint8_t bank_locator;
30 /* The 5th byte is '\0' for the end of string */
31 uint8_t serial[5];
32 /* The 19th byte is '\0' for the end of string */
33 uint8_t module_part_number[19];
34 uint16_t mod_id;
35 uint8_t mod_type;
36 uint8_t bus_width;
37} __packed;
38
39struct pei_memory_info {
40 uint8_t dimm_cnt;
41 /* Maximum num of dimm is 8 */
42 struct dimm_info dimm[8];
43} __packed;
44
Simon Glass268eefd2014-11-12 22:42:28 -070045struct memory_area {
46 uint64_t start;
47 uint64_t size;
48};
49
50struct memory_info {
51 int num_areas;
52 uint64_t total_memory;
53 uint64_t total_32bit_memory;
54 struct memory_area area[CONFIG_NR_DRAM_BANKS];
55};
56
Simon Glass7bf5b9e2015-01-01 16:18:07 -070057#define MAX_MTRR_REQUESTS 8
58
59/**
60 * A request for a memory region to be set up in a particular way. These
61 * requests are processed before board_init_r() is called. They are generally
62 * optional and can be ignored with some performance impact.
63 */
64struct mtrr_request {
65 int type; /* MTRR_TYPE_... */
66 uint64_t start;
67 uint64_t size;
68};
69
Simon Glass91efff52019-12-06 21:42:07 -070070/**
71 * struct mrc_output - holds the MRC data
72 *
73 * @buf: MRC training data to save for the next boot. This is set to point to
74 * the raw data after SDRAM init is complete. Then mrccache_setup()
75 * turns it into a proper cache record with a checksum
76 * @len: Length of @buf
77 * @cache: Resulting cache record
78 */
79struct mrc_output {
80 char *buf;
81 uint len;
82 struct mrc_data_container *cache;
83};
84
Simon Glass3ac47d72012-12-13 20:48:30 +000085/* Architecture-specific global data */
86struct arch_global_data {
Simon Glass9909bf32015-08-10 20:44:31 -060087 u64 gdt[X86_GDT_NUM_ENTRIES] __aligned(16);
Bin Meng47eac042015-01-22 11:29:40 +080088 struct global_data *gd_addr; /* Location of Global Data */
89 uint8_t x86; /* CPU family */
90 uint8_t x86_vendor; /* CPU vendor */
91 uint8_t x86_model;
92 uint8_t x86_mask;
Bin Meng035c1d22014-11-09 22:18:56 +080093 uint32_t x86_device;
Simon Glass6fa6e4a2013-02-28 19:26:12 +000094 uint64_t tsc_base; /* Initial value returned by rdtsc() */
Simon Glassed10a4f2019-10-20 21:37:47 -060095 bool tsc_inited; /* true if tsc is ready for use */
Simon Glass471919d2017-09-05 19:49:46 -060096 unsigned long clock_rate; /* Clock rate of timer in Hz */
Simon Glass347c05b2013-02-28 19:26:15 +000097 void *new_fdt; /* Relocated FDT */
Simon Glass1f4476c2014-11-06 13:20:10 -070098 uint32_t bist; /* Built-in self test value */
Simon Glass30580fc2014-11-12 22:42:23 -070099 enum pei_boot_mode_t pei_boot_mode;
Simon Glass60af0172014-11-12 22:42:24 -0700100 const struct pch_gpio_map *gpio_map; /* board GPIO map */
Simon Glass268eefd2014-11-12 22:42:28 -0700101 struct memory_info meminfo; /* Memory information */
Simon Glassd21f34e2016-03-11 22:07:26 -0700102 struct pei_memory_info pei_meminfo; /* PEI memory information */
Park, Aiden6e3cc362019-08-03 08:30:12 +0000103#ifdef CONFIG_USE_HOB
Bin Meng47eac042015-01-22 11:29:40 +0800104 void *hob_list; /* FSP HOB list */
Bin Meng005f0af2014-12-12 21:05:31 +0800105#endif
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700106 struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS];
107 int mtrr_req_count;
Bin Meng47eac042015-01-22 11:29:40 +0800108 int has_mtrr;
Simon Glass91efff52019-12-06 21:42:07 -0700109 /* MRC training data */
110 struct mrc_output mrc[MRC_TYPE_COUNT];
Simon Glassf95ad8c2015-08-04 12:33:57 -0600111 ulong table; /* Table pointer from previous loader */
Simon Glass37e706d2017-01-16 07:04:17 -0700112 int turbo_state; /* Current turbo state */
Simon Glassf64d6f72017-01-16 07:04:16 -0700113 struct irq_routing_table *pirq_routing_table;
Simon Glassf5bdce22019-12-06 21:41:41 -0700114 int dw_i2c_num_cards; /* Used by designware i2c driver */
Bin Meng322ec3e2016-05-11 07:44:59 -0700115#ifdef CONFIG_SEABIOS
116 u32 high_table_ptr;
117 u32 high_table_limit;
118#endif
Bin Mengef61f772017-04-21 07:24:32 -0700119#ifdef CONFIG_HAVE_ACPI_RESUME
Bin Meng2ee5b852017-04-21 07:24:33 -0700120 int prev_sleep_state; /* Previous sleep state ACPI_S0/1../5 */
Bin Meng353f5cb2017-04-21 07:24:47 -0700121 ulong backup_mem; /* Backup memory address for S3 */
Bin Mengef61f772017-04-21 07:24:32 -0700122#endif
Simon Glass26561da2019-12-06 21:42:21 -0700123#ifdef CONFIG_FSP_VERSION2
124 struct fsp_header *fsp_s_hdr; /* Pointer to FSP-S header */
125#endif
Simon Glassfaf08c72020-04-26 09:19:53 -0600126 ulong acpi_start; /* Start address of ACPI tables */
Simon Glass3ac47d72012-12-13 20:48:30 +0000127};
128
Graeme Russ3c28f482011-09-01 00:48:27 +0000129#endif
wdenk591dda52002-11-18 00:14:45 +0000130
Simon Glassd3887632012-12-13 20:49:27 +0000131#include <asm-generic/global_data.h>
132
133#ifndef __ASSEMBLY__
Simon Glass590aef72017-01-16 07:03:59 -0700134# if defined(CONFIG_EFI_APP) || CONFIG_IS_ENABLED(X86_64)
Simon Glass7f65c092015-07-31 09:31:35 -0600135
Simon Glass590aef72017-01-16 07:03:59 -0700136/* TODO(sjg@chromium.org): Consider using a fixed register for gd on x86_64 */
Simon Glass7f65c092015-07-31 09:31:35 -0600137#define gd global_data_ptr
138
139#define DECLARE_GLOBAL_DATA_PTR extern struct global_data *global_data_ptr
140# else
Simon Glass42081ce2013-06-11 11:14:52 -0700141static inline __attribute__((no_instrument_function)) gd_t *get_fs_gd_ptr(void)
Graeme Russ35368962011-12-31 22:58:15 +1100142{
143 gd_t *gd_ptr;
144
Simon Glass590aef72017-01-16 07:03:59 -0700145#if CONFIG_IS_ENABLED(X86_64)
146 asm volatile("fs mov 0, %0\n" : "=r" (gd_ptr));
147#else
Graeme Russ35368962011-12-31 22:58:15 +1100148 asm volatile("fs movl 0, %0\n" : "=r" (gd_ptr));
Simon Glass590aef72017-01-16 07:03:59 -0700149#endif
Graeme Russ35368962011-12-31 22:58:15 +1100150
151 return gd_ptr;
152}
153
154#define gd get_fs_gd_ptr()
Graeme Russ5fb91cc2010-10-07 20:03:29 +1100155
Simon Glass5d18dc92015-07-31 09:31:28 -0600156#define DECLARE_GLOBAL_DATA_PTR
Simon Glass7f65c092015-07-31 09:31:35 -0600157# endif
Simon Glass5d18dc92015-07-31 09:31:28 -0600158
Graeme Russ5fb91cc2010-10-07 20:03:29 +1100159#endif
160
wdenk591dda52002-11-18 00:14:45 +0000161#endif /* __ASM_GBL_DATA_H */