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git01.mediatek.com / filogic / uboot / e1e85444e75b0bd95b43e8c908bc573f3063e5f2 / . / configs / rock_defconfig
blob: bc97636d10bbb4228fc02056a85ead81d0d04d41 [file] [log] [blame]
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame^]2CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
3CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]4# CONFIG_SPL_USE_ARCH_MEMCPY is not set
5# CONFIG_SPL_USE_ARCH_MEMSET is not set
6CONFIG_ARCH_ROCKCHIP=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]7CONFIG_SYS_TEXT_BASE=0x60000000
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]8CONFIG_SYS_MALLOC_F_LEN=0x2000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]9CONFIG_NR_DRAM_BANKS=1
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]10CONFIG_ENV_OFFSET=0x3F8000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]11CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]12CONFIG_SPL_TEXT_BASE=0x10080800
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]13CONFIG_ROCKCHIP_RK3188=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]14CONFIG_TARGET_ROCK=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]15CONFIG_SPL_STACK_R_ADDR=0x60080000
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]16CONFIG_DEBUG_UART_BASE=0x20064000
17CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]18CONFIG_DEBUG_UART=y
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]19CONFIG_SYS_LOAD_ADDR=0x60800800
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]20CONFIG_USE_PREBOOT=y
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]21CONFIG_DEFAULT_FDT_FILE="rk3188-radxarock.dtb"
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]22# CONFIG_DISPLAY_CPUINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]23CONFIG_DISPLAY_BOARDINFO_LATE=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]24CONFIG_SPL_STACK_R=y
25CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Maxime Ripard24336442017-08-24 11:52:32 +0200[diff] [blame]26CONFIG_RANDOM_UUID=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]27CONFIG_CMD_I2C=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]28CONFIG_CMD_MMC=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]29CONFIG_CMD_SPI=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]30# CONFIG_CMD_SETEXPR is not set
31CONFIG_CMD_CACHE=y
32CONFIG_CMD_TIME=y
33CONFIG_CMD_REGULATOR=y
34CONFIG_SPL_OF_CONTROL=y
35CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
36CONFIG_SPL_OF_PLATDATA=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]37CONFIG_ENV_IS_IN_MMC=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]38CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]39CONFIG_REGMAP=y
40CONFIG_SYSCON=y
41# CONFIG_SPL_SIMPLE_BUS is not set
42CONFIG_CLK=y
43CONFIG_ROCKCHIP_GPIO=y
44CONFIG_SYS_I2C_ROCKCHIP=y
45CONFIG_LED=y
46CONFIG_MMC_DW=y
47CONFIG_MMC_DW_ROCKCHIP=y
Miquel Raynal2e35dbb2019-10-03 19:50:05 +0200[diff] [blame]48CONFIG_MTD=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]49CONFIG_SF_DEFAULT_SPEED=20000000
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]50CONFIG_PINCTRL=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]51CONFIG_DM_PMIC=y
52# CONFIG_SPL_PMIC_CHILDREN is not set
53CONFIG_PMIC_ACT8846=y
54CONFIG_REGULATOR_ACT8846=y
55CONFIG_DM_REGULATOR_FIXED=y
56CONFIG_RAM=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]57CONFIG_DEBUG_UART_SHIFT=2
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]58CONFIG_SYSRESET=y
Tom Rini2cbc1202018-04-28 10:45:55 -0400[diff] [blame]59CONFIG_TIMER=y
60CONFIG_SPL_TIMER=y
61CONFIG_ROCKCHIP_TIMER=y
Adam Fordd4183d62018-01-02 10:39:52 -0600[diff] [blame]62CONFIG_USB=y
63CONFIG_ROCKCHIP_USB2_PHY=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]64CONFIG_SPL_TINY_MEMSET=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]65CONFIG_CMD_DHRYSTONE=y
66CONFIG_ERRNO_STR=y