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git01.mediatek.com / filogic / uboot / 3ef67aec8ce027e1b028dc2cf66b40d91b09d86d / . / configs / rock_defconfig
blob: 96bc4ee8142565d074947cf913ed011c9c424172 [file] [log] [blame]
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]1CONFIG_ARM=y
2# CONFIG_SPL_USE_ARCH_MEMCPY is not set
3# CONFIG_SPL_USE_ARCH_MEMSET is not set
4CONFIG_ARCH_ROCKCHIP=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]5CONFIG_SYS_TEXT_BASE=0x60000000
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]6CONFIG_SYS_MALLOC_F_LEN=0x2000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]7CONFIG_NR_DRAM_BANKS=1
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]8CONFIG_ENV_OFFSET=0x3F8000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]9CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]10CONFIG_SPL_TEXT_BASE=0x10080800
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]11CONFIG_ROCKCHIP_RK3188=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]12CONFIG_TARGET_ROCK=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]13CONFIG_SPL_STACK_R_ADDR=0x60080000
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]14CONFIG_DEBUG_UART_BASE=0x20064000
15CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]16CONFIG_DEBUG_UART=y
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]17CONFIG_SYS_LOAD_ADDR=0x60800800
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]18CONFIG_USE_PREBOOT=y
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]19CONFIG_DEFAULT_FDT_FILE="rk3188-radxarock.dtb"
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]20# CONFIG_DISPLAY_CPUINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]21CONFIG_DISPLAY_BOARDINFO_LATE=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]22CONFIG_SPL_STACK_R=y
23CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Maxime Ripard24336442017-08-24 11:52:32 +0200[diff] [blame]24CONFIG_RANDOM_UUID=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]25CONFIG_CMD_I2C=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]26CONFIG_CMD_MMC=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]27CONFIG_CMD_SPI=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]28# CONFIG_CMD_SETEXPR is not set
29CONFIG_CMD_CACHE=y
30CONFIG_CMD_TIME=y
31CONFIG_CMD_REGULATOR=y
32CONFIG_SPL_OF_CONTROL=y
33CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
34CONFIG_SPL_OF_PLATDATA=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]35CONFIG_ENV_IS_IN_MMC=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]36CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]37CONFIG_REGMAP=y
38CONFIG_SYSCON=y
39# CONFIG_SPL_SIMPLE_BUS is not set
40CONFIG_CLK=y
41CONFIG_ROCKCHIP_GPIO=y
42CONFIG_SYS_I2C_ROCKCHIP=y
43CONFIG_LED=y
44CONFIG_MMC_DW=y
45CONFIG_MMC_DW_ROCKCHIP=y
Miquel Raynal2e35dbb2019-10-03 19:50:05 +0200[diff] [blame]46CONFIG_MTD=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]47CONFIG_SF_DEFAULT_SPEED=20000000
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]48CONFIG_PINCTRL=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]49CONFIG_DM_PMIC=y
50# CONFIG_SPL_PMIC_CHILDREN is not set
51CONFIG_PMIC_ACT8846=y
52CONFIG_REGULATOR_ACT8846=y
53CONFIG_DM_REGULATOR_FIXED=y
54CONFIG_RAM=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]55CONFIG_DEBUG_UART_SHIFT=2
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]56CONFIG_SYSRESET=y
Tom Rini2cbc1202018-04-28 10:45:55 -0400[diff] [blame]57CONFIG_TIMER=y
58CONFIG_SPL_TIMER=y
59CONFIG_ROCKCHIP_TIMER=y
Adam Fordd4183d62018-01-02 10:39:52 -0600[diff] [blame]60CONFIG_USB=y
61CONFIG_ROCKCHIP_USB2_PHY=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]62CONFIG_SPL_TINY_MEMSET=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]63CONFIG_CMD_DHRYSTONE=y
64CONFIG_ERRNO_STR=y