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git01.mediatek.com / filogic / uboot / e17596d0db84c272690fc72b3667ffe142544cbb / . / arch / arm / dts / k3-am62a7-sk-u-boot.dtsi
blob: cf938c43b832e58b8dbec43c960d13e077d9c9ff [file] [log] [blame]
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Common AM62A EVM dts file for SPLs
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
5 */
6
7/ {
8 chosen {
9 stdout-path = "serial2:115200n8";
10 tick-timer = &timer1;
11 };
12
13 memory@80000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]14 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]15 };
16};
17
18&cbass_main{
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]19 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]20
21 timer1: timer@2400000 {
22 compatible = "ti,omap5430-timer";
23 reg = <0x00 0x2400000 0x00 0x80>;
24 ti,timer-alwon;
25 clock-frequency = <25000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]26 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]27 };
28};
29
30&dmss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]31 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]32};
33
34&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]36};
37
38&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]40};
41
42&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]44};
45
46&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]47 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]48};
49
50&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]52};
53
54&wkup_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]55 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]56};
57
58&chipid {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]60};
61
62&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]64};
65
66&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]68};
69
70&main_uart0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]71 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]72};
73
74&main_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]76};
77
78&cbass_mcu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]80};
81
82&cbass_wakeup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]84};
85
86&mcu_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]87 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]88};
89
90&wkup_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]92};
93
94&main_gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]96};
97
98&main_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]99 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]100};
101
102&main_i2c0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]104};
105
106&main_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]107 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]108};
109
110&main_i2c1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]111 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]112};
113
114&exp1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]115 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]116};
117
118&sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]119 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]120};
121
122&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]123 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]124};
125
126&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]127 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]128};
129
130&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]131 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]132 k3_sysreset: sysreset-controller {
133 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]134 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]135 };
136};
137
138&vdd_mmc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]139 bootph-pre-ram;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]140};