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git01.mediatek.com / filogic / uboot / e17596d0db84c272690fc72b3667ffe142544cbb / . / arch / arm / dts / at91sam9g45-gurnard.dts
blob: cf0c19c02c5af7a66b2051452720bbcb307d0b94 [file] [log] [blame]
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]1/*
2 * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8/dts-v1/;
9#include "at91sam9g45.dtsi"
10
11/ {
12 model = "Bluewater Systems Gurnard";
13 compatible = "atmel,at91sam9g45", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs";
17 stdout-path = "serial0:115200n8";
18 };
19
20 memory {
21 reg = <0x20000000 0x8000000>;
22 };
23
24 clocks {
25 slow_xtal {
26 clock-frequency = <32768>;
27 };
28
29 main_xtal {
30 clock-frequency = <18432000>;
31 };
32 };
33
34 ahb {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-all;
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]36
37 fb@0x00500000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-all;
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]39 status = "okay";
40 display-timings {
41 rev1 {
42 clock-frequency = <4166666>;
43 hactive = <480>;
44 vactive = <272>;
45 hfront-porch = <1>;
46 hback-porch = <1>;
47 hsync-len = <1>;
48 vback-porch = <4>;
49 vfront-porch = <2>;
50 vsync-len = <1>;
51 hsync-active = <0>;
52 vsync-active = <0>;
53 };
54
55 rev2 {
56 clock-frequency = <4166666>;
57 hactive = <480>;
58 vactive = <272>;
59 hfront-porch = <2>;
60 hback-porch = <2>;
61 hsync-len = <10>;
62 vback-porch = <2>;
63 vfront-porch = <2>;
64 vsync-len = <10>;
65 hsync-active = <0>;
66 vsync-active = <0>;
67 };
68 };
69 };
70
71 apb {
72 pinctrl@fffff400 {
73 board {
74 pinctrl_pck0_as_mck: pck0_as_mck {
75 atmel,pins =
76 <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC1 periph B */
77 };
78
79 };
80
81 mmc0_slot1 {
82 pinctrl_board_mmc0_slot1: mmc0_slot1-board {
83 atmel,pins =
84 <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PC9 gpio CD pin pull up and deglitch */
85 };
86 };
87 };
88
89 dbgu: serial@ffffee00 {
90 status = "okay";
91 };
92
93 macb0: ethernet@fffbc000 {
94 phy-mode = "rmii";
95 status = "okay";
96 };
97
98 mmc0: mmc@fff80000 {
99 pinctrl-0 = <
100 &pinctrl_board_mmc0_slot1
101 &pinctrl_mmc0_slot0_clk_cmd_dat0
102 &pinctrl_mmc0_slot0_dat1_3>;
103 status = "okay";
104 slot@1 {
105 reg = <1>;
106 bus-width = <4>;
107 cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>;
108 };
109 };
110
111 ssc0: ssc@fff9c000 {
112 status = "okay";
113 pinctrl-0 = <&pinctrl_ssc0_tx>;
114 };
115
116 spi0: spi@fffa4000 {
117 cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
Eugen Hristeveb8f2732020-10-26 10:39:51 +0200[diff] [blame]118 mtd_dataflash@1 {
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]119 compatible = "atmel,at45", "atmel,dataflash";
120 spi-max-frequency = <50000000>;
121 reg = <1>;
122 };
123 };
124
125 shdwc@fffffd10 {
126 atmel,wakeup-counter = <10>;
127 atmel,wakeup-rtt-timer;
128 };
129
130 rtc@fffffd20 {
131 atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
132 status = "okay";
133 };
134
135 watchdog@fffffd40 {
136 status = "okay";
137 };
138
139 gpbr: syscon@fffffd60 {
140 status = "okay";
141 };
142 };
143
144 nand0: nand@40000000 {
145 nand-bus-width = <8>;
146 nand-ecc-mode = "hardware";
147 nand-on-flash-bbt;
148 status = "okay";
149 };
150
151 usb1: ehci@00800000 {
152 atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
153 status = "okay";
154 };
155 };
156
157};