| Durai Manickam KR | 2e7bc61 | 2022-04-04 11:23:18 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Configuration settings for the SAM9X60 CURIOSITY board. |
| 4 | * |
| 5 | * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries |
| 6 | * |
| 7 | * Author: Durai Manickam KR <durai.manickamkr@microchip.com> |
| 8 | */ |
| 9 | |
| 10 | #ifndef __CONFIG_H__ |
| 11 | #define __CONFIG_H__ |
| 12 | |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 13 | #define CFG_SYS_AT91_SLOW_CLOCK 32768 |
| 14 | #define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ |
| Durai Manickam KR | 2e7bc61 | 2022-04-04 11:23:18 +0530 | [diff] [blame] | 15 | |
| Tom Rini | 7abe2a9 | 2022-12-04 10:14:02 -0500 | [diff] [blame] | 16 | #define CFG_USART_BASE ATMEL_BASE_DBGU |
| Tom Rini | e111a12 | 2022-12-04 10:14:03 -0500 | [diff] [blame^] | 17 | #define CFG_USART_ID 0 /* ignored in arm */ |
| Durai Manickam KR | 2e7bc61 | 2022-04-04 11:23:18 +0530 | [diff] [blame] | 18 | |
| 19 | /* SDRAM */ |
| Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 20 | #define CFG_SYS_SDRAM_BASE 0x20000000 |
| 21 | #define CFG_SYS_SDRAM_SIZE 0x8000000 /* 128 MB */ |
| Durai Manickam KR | 2e7bc61 | 2022-04-04 11:23:18 +0530 | [diff] [blame] | 22 | |
| Durai Manickam KR | 2e7bc61 | 2022-04-04 11:23:18 +0530 | [diff] [blame] | 23 | #endif |