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git01.mediatek.com / filogic / uboot / dfff7a2c2ab694f0f54b8968c5dc0ccc1e60c32a / . / board / Marvell / include / memory.h
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wdenk5da7f2f2004-01-03 00:43:19 +0000[diff] [blame]1/* Memory.h - Memory mappings and remapping functions declarations */
2
3/* Copyright - Galileo technology. */
4
5#ifndef __INCmemoryh
6#define __INCmemoryh
7
8/* includes */
9
10#include "core.h"
11
12/* defines */
13
14#define DONT_MODIFY 0xffffffff
15#define PARITY_SUPPORT 0x40000000
16#define MINIMUM_MEM_BANK_SIZE 0x10000
17#define MINIMUM_DEVICE_WINDOW_SIZE 0x10000
18#define MINIMUM_PCI_WINDOW_SIZE 0x10000
19#define MINIMUM_ACCESS_WIN_SIZE 0x10000
20
21#define _8BIT 0x00000000
22#define _16BIT 0x00100000
23#define _32BIT 0x00200000
24#define _64BIT 0x00300000
25
26/* typedefs */
27
28 typedef struct deviceParam
29{ /* boundary values */
30 unsigned int turnOff; /* 0x0 - 0xf */
31 unsigned int acc2First; /* 0x0 - 0x1f */
32 unsigned int acc2Next; /* 0x0 - 0x1f */
33 unsigned int ale2Wr; /* 0x0 - 0xf */
34 unsigned int wrLow; /* 0x0 - 0xf */
35 unsigned int wrHigh; /* 0x0 - 0xf */
36 unsigned int badrSkew; /* 0x0 - 0x2 */
37 unsigned int DPEn; /* 0x0 - 0x1 */
38 unsigned int deviceWidth; /* in Bytes */
39} DEVICE_PARAM;
40
41
42typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
43typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
44
45/*typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \
46 MEM_REGION3,MEM_REGION4,MEM_REGION5, \
47 MEM_REGION6,MEM_REGION7} \
48 MEMORY_PROTECT_REGION;*/
49/* There are four possible windows that can be defined as protected */
50typedef enum _memoryProtectWindow{MEM_WINDOW0,MEM_WINDOW1,MEM_WINDOW2,
51 MEM_WINDOW3
52 } MEMORY_PROTECT_WINDOW;
53/* When defining a protected window , this paramter indicates whether it
54 is accessible or not */
55typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \
56 MEMORY_ACCESS;
57typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \
58 MEMORY_ACCESS_WRITE;
59typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \
60 MEMORY_CACHE_PROTECT;
61typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \
62 MEMORY_SNOOP_TYPE;
63typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \
64 MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \
65 MEMORY_SNOOP_REGION;
66
67/* There are 21 memory windows dedicated for the varios interfaces (PCI,
68 devCS (devices), CS(DDR), interenal registers and SRAM) used by the CPU's
69 address decoding mechanism. */
70typedef enum _memoryWindow {CS_0_WINDOW = BIT0, CS_1_WINDOW = BIT1,
71 CS_2_WINDOW = BIT2, CS_3_WINDOW = BIT3,
72 DEVCS_0_WINDOW = BIT4, DEVCS_1_WINDOW = BIT5,
73 DEVCS_2_WINDOW = BIT6, DEVCS_3_WINDOW = BIT7,
74 BOOT_CS_WINDOW = BIT8, PCI_0_IO_WINDOW = BIT9,
75 PCI_0_MEM0_WINDOW = BIT10,
76 PCI_0_MEM1_WINDOW = BIT11,
77 PCI_0_MEM2_WINDOW = BIT12,
78 PCI_0_MEM3_WINDOW = BIT13, PCI_1_IO_WINDOW = BIT14,
79 PCI_1_MEM0_WINDOW = BIT15, PCI_1_MEM1_WINDOW =BIT16,
80 PCI_1_MEM2_WINDOW = BIT17, PCI_1_MEM3_WINDOW =BIT18,
81 INTEGRATED_SRAM_WINDOW = BIT19,
82 INTERNAL_SPACE_WINDOW = BIT20,
83 ALL_WINDOWS = 0X1FFFFF
84 } MEMORY_WINDOW;
85
86typedef enum _memoryWindowStatus {MEM_WINDOW_ENABLED,MEM_WINDOW_DISABLED
87 } MEMORY_WINDOW_STATUS;
88
89
90typedef enum _pciMemWindow{PCI_0_IO,PCI_0_MEM0,PCI_0_MEM1,PCI_0_MEM2,PCI_0_MEM3
91#ifdef INCLUDE_PCI_1
92 ,PCI_1_IO,PCI_1_MEM0,PCI_1_MEM1,PCI_1_MEM2,PCI_1_MEM3
93#endif /* INCLUDE_PCI_1 */
94 } PCI_MEM_WINDOW;
95
96
97/* -------------------------------------------------------------------------------------------------*/
98
99/* functions */
100unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
101unsigned int memoryGetDeviceBaseAddress(DEVICE device);
102/* New at MV6436x */
103unsigned int MemoryGetPciBaseAddr(PCI_MEM_WINDOW pciWindow);
104unsigned int memoryGetBankSize(MEMORY_BANK bank);
105unsigned int memoryGetDeviceSize(DEVICE device);
106unsigned int memoryGetDeviceWidth(DEVICE device);
107/* New at MV6436x */
108unsigned int gtMemoryGetPciWindowSize(PCI_MEM_WINDOW pciWindow);
109
110/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
111bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
112/* Set a new base and size for one of the memory banks (CS0 - CS3) */
113bool gtMemorySetMemoryBank(MEMORY_BANK bank, unsigned int bankBase,
114 unsigned int bankSize);
115bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
116
117/* Change the Internal Register Base Address to a new given Address. */
118bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
119/* returns internal Register Space Base Address. */
120unsigned int memoryGetInternalRegistersSpace(void);
121
122/* Returns the integrated SRAM Base Address. */
123unsigned int memoryGetInternalSramBaseAddr(void);
124/* -------------------------------------------------------------------------------------------------*/
125
126/* Set new base address for the integrated SRAM. */
127void memorySetInternalSramBaseAddr(unsigned int sramBaseAddress);
128/* -------------------------------------------------------------------------------------------------*/
129
130/* Delete a protection feature to a given space. */
131void memoryDisableProtectRegion(MEMORY_PROTECT_WINDOW window);
132/* -------------------------------------------------------------------------------------------------*/
133
134/* Writes a new remap value to the remap register */
135unsigned int memorySetPciRemapValue(PCI_MEM_WINDOW memoryWindow,
136 unsigned int remapValueHigh,
137 unsigned int remapValueLow);
138/* -------------------------------------------------------------------------------------------------*/
139
140/* Configurate the protection feature to a given space. */
141bool memorySetProtectRegion(MEMORY_PROTECT_WINDOW window,
142 MEMORY_ACCESS gtMemoryAccess,
143 MEMORY_ACCESS_WRITE gtMemoryWrite,
144 MEMORY_CACHE_PROTECT cacheProtection,
145 unsigned int baseAddress,
146 unsigned int size);
147
148/* Configurate the protection feature to a given space. */
149/*bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
150 MEMORY_ACCESS memoryAccess,
151 MEMORY_ACCESS_WRITE memoryWrite,
152 MEMORY_CACHE_PROTECT cacheProtection,
153 unsigned int baseAddress,
154 unsigned int regionLength); */
155/* Configurate the snoop feature to a given space. */
156bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
157 MEMORY_SNOOP_TYPE snoopType,
158 unsigned int baseAddress,
159 unsigned int regionLength);
160
161bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
162bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
163bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
164/* Set a new base and size for one of the PCI windows. */
165bool memorySetPciWindow(PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
166 unsigned int pciWindowSize);
167
168/* Disable or enable one of the 21 windows dedicated for the CPU's
169 address decoding mechanism */
170void MemoryDisableWindow(MEMORY_WINDOW window);
171void MemoryEnableWindow (MEMORY_WINDOW window);
172MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus(MEMORY_WINDOW window);
173#endif /* __INCmemoryh */