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Wolfgang Denk83c15852006-10-24 14:21:16 +02001/*
2 * Copyright (C) 2006 Atmel Corporation
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denk83c15852006-10-24 14:21:16 +02005 */
6#ifndef __ASM_AVR32_SDRAM_H
7#define __ASM_AVR32_SDRAM_H
8
Haavard Skinnemoen23f62f12008-05-19 11:36:28 +02009struct sdram_config {
10 /* Number of data bits. */
11 enum {
Haavard Skinnemoenbaa593c2008-08-30 17:28:36 +020012 SDRAM_DATA_16BIT = 16,
13 SDRAM_DATA_32BIT = 32,
Haavard Skinnemoen23f62f12008-05-19 11:36:28 +020014 } data_bits;
15
16 /* Number of address bits */
17 uint8_t row_bits, col_bits, bank_bits;
18
19 /* SDRAM timings in cycles */
20 uint8_t cas, twr, trc, trp, trcd, tras, txsr;
Haavard Skinnemoend5d6ca62008-01-23 17:20:14 +010021
22 /* SDRAM refresh period in cycles */
23 unsigned long refresh_period;
Wolfgang Denk83c15852006-10-24 14:21:16 +020024};
25
Haavard Skinnemoen23f62f12008-05-19 11:36:28 +020026/*
27 * Attempt to initialize the SDRAM controller using the specified
28 * parameters. Return the expected size of the memory area based on
29 * the number of address and data bits.
30 *
31 * The caller should verify that the configuration is correct by
32 * running a memory test, e.g. get_ram_size().
33 */
34extern unsigned long sdram_init(void *sdram_base,
35 const struct sdram_config *config);
Wolfgang Denk83c15852006-10-24 14:21:16 +020036
37#endif /* __ASM_AVR32_SDRAM_H */