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git01.mediatek.com / filogic / uboot / df71c312909c046f889c18ba3e8451f6031179b8 / . / arch / arm / mach-davinci / include / mach / pll_defs.h
blob: e38fafd7c80ac27910973f6c436b65af87c78af3 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Heiko Schocherf1084d62011-11-01 20:00:31 +0000[diff] [blame]2/*
3 * Copyright (C) 2011
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
Heiko Schocherf1084d62011-11-01 20:00:31 +0000[diff] [blame]5 */
6#ifndef _DV_PLL_DEFS_H_
7#define _DV_PLL_DEFS_H_
8
9struct dv_pll_regs {
10 unsigned int pid; /* 0x00 */
11 unsigned char rsvd0[224]; /* 0x04 */
12 unsigned int rstype; /* 0xe4 */
13 unsigned char rsvd1[24]; /* 0xe8 */
14 unsigned int pllctl; /* 0x100 */
15 unsigned char rsvd2[4]; /* 0x104 */
16 unsigned int secctl; /* 0x108 */
17 unsigned int rv; /* 0x10c */
18 unsigned int pllm; /* 0x110 */
19 unsigned int prediv; /* 0x114 */
20 unsigned int plldiv1; /* 0x118 */
21 unsigned int plldiv2; /* 0x11c */
22 unsigned int plldiv3; /* 0x120 */
23 unsigned int oscdiv1; /* 0x124 */
24 unsigned int postdiv; /* 0x128 */
25 unsigned int bpdiv; /* 0x12c */
26 unsigned char rsvd5[8]; /* 0x130 */
27 unsigned int pllcmd; /* 0x138 */
28 unsigned int pllstat; /* 0x13c */
29 unsigned int alnctl; /* 0x140 */
30 unsigned int dchange; /* 0x144 */
31 unsigned int cken; /* 0x148 */
32 unsigned int ckstat; /* 0x14c */
33 unsigned int systat; /* 0x150 */
34 unsigned char rsvd6[12]; /* 0x154 */
35 unsigned int plldiv4; /* 0x160 */
36 unsigned int plldiv5; /* 0x164 */
37 unsigned int plldiv6; /* 0x168 */
38 unsigned int plldiv7; /* 0x16C */
39 unsigned int plldiv8; /* 0x170 */
40 unsigned int plldiv9; /* 0x174 */
41};
42
Heiko Schocher34061e82011-11-15 10:00:02 -0500[diff] [blame]43#define PLL_MASTER_LOCK (1 << 4)
44
45#define PLLCTL_CLOCK_MODE_SHIFT 8
Heiko Schocherf1084d62011-11-01 20:00:31 +0000[diff] [blame]46#define PLLCTL_PLLEN (1 << 0)
47#define PLLCTL_PLLPWRDN (1 << 1)
48#define PLLCTL_PLLRST (1 << 3)
Heiko Schocher34061e82011-11-15 10:00:02 -0500[diff] [blame]49#define PLLCTL_PLLDIS (1 << 4)
Heiko Schocherf1084d62011-11-01 20:00:31 +0000[diff] [blame]50#define PLLCTL_PLLENSRC (1 << 5)
51#define PLLCTL_RES_9 (1 << 8)
Heiko Schocher34061e82011-11-15 10:00:02 -0500[diff] [blame]52#define PLLCTL_EXTCLKSRC (1 << 9)
53
Ben Gardinerb2a47522012-01-16 07:43:15 +0000[diff] [blame]54#define PLL_DIVEN (1 << 15)
55#define PLL_POSTDEN PLL_DIVEN
Heiko Schocher34061e82011-11-15 10:00:02 -0500[diff] [blame]56
57#define PLL_SCSCFG3_DIV45PENA (1 << 2)
58#define PLL_SCSCFG3_EMA_CLKSRC (1 << 1)
59
60#define PLL_RSTYPE_POR (1 << 0)
61#define PLL_RSTYPE_XWRST (1 << 1)
Heiko Schocherf1084d62011-11-01 20:00:31 +0000[diff] [blame]62
63#define PLLSECCTL_TINITZ (1 << 16)
64#define PLLSECCTL_TENABLE (1 << 17)
65#define PLLSECCTL_TENABLEDIV (1 << 18)
66#define PLLSECCTL_STOPMODE (1 << 22)
67
68#define PLLCMD_GOSET (1 << 0)
Heiko Schocher34061e82011-11-15 10:00:02 -0500[diff] [blame]69#define PLLCMD_GOSTAT (1 << 0)
Heiko Schocherf1084d62011-11-01 20:00:31 +0000[diff] [blame]70
71#define PLL0_LOCK 0x07000000
72#define PLL1_LOCK 0x07000000
73
74#define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
75#define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
76
Heiko Schocher59214f82011-11-01 20:00:33 +0000[diff] [blame]77#define ARM_PLLDIV (offsetof(struct dv_pll_regs, plldiv2))
78#define DDR_PLLDIV (offsetof(struct dv_pll_regs, plldiv7))
Heiko Schocher109f5482011-11-01 20:00:34 +0000[diff] [blame]79#define SPI_PLLDIV (offsetof(struct dv_pll_regs, plldiv4))
Heiko Schocher59214f82011-11-01 20:00:33 +0000[diff] [blame]80
81unsigned int davinci_clk_get(unsigned int div);
Heiko Schocherf1084d62011-11-01 20:00:31 +0000[diff] [blame]82#endif /* _DV_PLL_DEFS_H_ */