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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
gaurav rana9d171da2015-02-27 09:43:49 +05302/*
3 * Copyright 2015 Freescale Semiconductor, Inc.
gaurav rana9d171da2015-02-27 09:43:49 +05304 */
5
6#ifndef _FSL_SFP_SNVS_
7#define _FSL_SFP_SNVS_
8
gaurav rana9d171da2015-02-27 09:43:49 +05309#include <config.h>
10#include <asm/io.h>
11
12#ifdef CONFIG_SYS_FSL_SRK_LE
13#define srk_in32(a) in_le32(a)
14#else
15#define srk_in32(a) in_be32(a)
16#endif
17
18#ifdef CONFIG_SYS_FSL_SFP_LE
19#define sfp_in32(a) in_le32(a)
20#define sfp_out32(a, v) out_le32(a, v)
21#define sfp_in16(a) in_le16(a)
22#elif defined(CONFIG_SYS_FSL_SFP_BE)
23#define sfp_in32(a) in_be32(a)
24#define sfp_out32(a, v) out_be32(a, v)
25#define sfp_in16(a) in_be16(a)
gaurav rana9d171da2015-02-27 09:43:49 +053026#endif
27
28/* Number of SRKH registers */
29#define NUM_SRKH_REGS 8
30
Saksham Jain62888be2016-03-23 16:24:32 +053031#if defined(CONFIG_SYS_FSL_SFP_VER_3_2) || \
32 defined(CONFIG_SYS_FSL_SFP_VER_3_4)
gaurav rana9d171da2015-02-27 09:43:49 +053033struct ccsr_sfp_regs {
34 u32 ospr; /* 0x200 */
35 u32 ospr1; /* 0x204 */
36 u32 reserved1[4];
37 u32 fswpr; /* 0x218 FSL Section Write Protect */
38 u32 fsl_uid; /* 0x21c FSL UID 0 */
39 u32 fsl_uid_1; /* 0x220 FSL UID 0 */
40 u32 reserved2[12];
41 u32 srk_hash[8]; /* 0x254 Super Root Key Hash */
42 u32 oem_uid; /* 0x274 OEM UID 0*/
43 u32 oem_uid_1; /* 0x278 OEM UID 1*/
44 u32 oem_uid_2; /* 0x27c OEM UID 2*/
45 u32 oem_uid_3; /* 0x280 OEM UID 3*/
46 u32 oem_uid_4; /* 0x284 OEM UID 4*/
47 u32 reserved3[8];
48};
49#elif defined(CONFIG_SYS_FSL_SFP_VER_3_0)
50struct ccsr_sfp_regs {
51 u32 ospr; /* 0x200 */
52 u32 reserved0[14];
53 u32 srk_hash[NUM_SRKH_REGS]; /* 0x23c Super Root Key Hash */
54 u32 oem_uid; /* 0x9c OEM Unique ID */
55 u8 reserved2[0x04];
56 u32 ovpr; /* 0xA4 Intent To Secure */
57 u8 reserved4[0x08];
58 u32 fsl_uid; /* 0xB0 FSL Unique ID */
59 u8 reserved5[0x04];
60 u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */
61 u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */
62
63};
64#else
65struct ccsr_sfp_regs {
66 u8 reserved0[0x40];
67 u32 ospr; /* 0x40 OEM Security Policy Register */
68 u8 reserved2[0x38];
69 u32 srk_hash[8]; /* 0x7c Super Root Key Hash */
70 u32 oem_uid; /* 0x9c OEM Unique ID */
71 u8 reserved4[0x4];
72 u32 ovpr; /* 0xA4 OEM Validation Policy Register */
73 u8 reserved8[0x8];
74 u32 fsl_uid; /* 0xB0 FSL Unique ID */
75};
76#endif
Sumit Garg44e50a52016-09-07 12:17:34 -040077
gaurav rana9d171da2015-02-27 09:43:49 +053078#define ITS_MASK 0x00000004
79#define ITS_BIT 2
Sumit Garg44e50a52016-09-07 12:17:34 -040080
81#if defined(CONFIG_SYS_FSL_SFP_VER_3_4)
82#define OSPR_KEY_REVOC_SHIFT 9
83#define OSPR_KEY_REVOC_MASK 0x0000fe00
84#else
85#define OSPR_KEY_REVOC_SHIFT 13
86#define OSPR_KEY_REVOC_MASK 0x0000e000
87#endif /* CONFIG_SYS_FSL_SFP_VER_3_4 */
gaurav rana9d171da2015-02-27 09:43:49 +053088
89#endif