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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +09002/*
3 * include/configs/gose.h
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +09006 */
7
8#ifndef __GOSE_H
9#define __GOSE_H
10
Nobuhiro Iwamatsub6169ac2014-11-10 14:34:07 +090011#include "rcar-gen2-common.h"
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090012
Marek Vasut2d6dabc2018-04-23 20:24:10 +020013#define STACK_AREA_SIZE 0x00100000
14#define LOW_LEVEL_MERAM_STACK \
Tom Rini4ddbade2022-05-25 12:16:03 -040015 (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090016
17/* MEMORY */
Nobuhiro Iwamatsub6169ac2014-11-10 14:34:07 +090018#define RCAR_GEN2_SDRAM_BASE 0x40000000
Marek Vasut2d6dabc2018-04-23 20:24:10 +020019#define RCAR_GEN2_SDRAM_SIZE (1048u * 1024 * 1024)
20#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024)
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090021
Nobuhiro Iwamatsueef1f232014-11-06 15:42:24 +090022/* SH Ether */
Tom Rini9996ab82022-12-04 10:13:52 -050023#define CFG_SH_ETHER_USE_PORT 0
Tom Rini45ec5fd2022-12-04 10:13:50 -050024#define CFG_SH_ETHER_PHY_ADDR 0x1
Tom Rinib210dc12022-12-04 10:13:51 -050025#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
Tom Rini872054f2022-12-04 10:13:49 -050026#define CFG_SH_ETHER_CACHE_WRITEBACK
Tom Rinia44cb162022-12-04 10:13:48 -050027#define CFG_SH_ETHER_CACHE_INVALIDATE
Tom Rinidd2eba02022-12-04 10:13:47 -050028#define CFG_SH_ETHER_ALIGNE_SIZE 64
Nobuhiro Iwamatsueef1f232014-11-06 15:42:24 +090029
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090030/* Board Clock */
Nobuhiro Iwamatsu87adc0a2014-11-06 15:42:25 +090031
Tom Rinic9edebe2022-12-04 10:03:50 -050032#define CFG_EXTRA_ENV_SETTINGS \
Marek Vasut4f34a4b2018-11-27 00:19:03 +010033 "bootm_size=0x10000000\0"
Nobuhiro Iwamatsue02f1742014-12-02 16:52:24 +090034
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090035#endif /* __GOSE_H */