blob: d4e0f677e67b379a663bdb662c09f05dec140308 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +09002/*
3 * include/configs/blanche.h
4 * This file is blanche board configuration.
5 *
6 * Copyright (C) 2016 Renesas Electronics Corporation
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +09007 */
8
9#ifndef __BLANCHE_H
10#define __BLANCHE_H
11
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090012#include "rcar-gen2-common.h"
13
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090014/* STACK */
Marek Vasut927b1e32018-04-30 14:10:36 +020015#define STACK_AREA_SIZE 0x00100000
16#define LOW_LEVEL_MERAM_STACK \
Tom Rini4ddbade2022-05-25 12:16:03 -040017 (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090018
19/* MEMORY */
20#define RCAR_GEN2_SDRAM_BASE 0x40000000
21#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
22#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
23
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090024/* FLASH */
Tom Riniaf1a3e92022-12-02 16:42:31 -050025#if defined(CONFIG_MTD_NOR_FLASH)
Tom Rini6a5dccc2022-11-16 13:10:41 -050026#define CFG_SYS_FLASH_BASE 0x00000000
27#define CFG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
28#define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) }
29#define CFG_SYS_FLASH_BANKS_SIZES { (CFG_SYS_FLASH_SIZE) }
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090030#endif
31
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090032/* Board Clock */
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090033
34/* ENV setting */
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090035
masakazu.mochizuki.wd@hitachi.com9d0e9372016-04-12 17:11:41 +090036#endif /* __BLANCHE_H */