Heiko Thiery | 05a3d95 | 2022-01-31 17:30:45 +0100 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_IMX8M=y |
Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 3 | CONFIG_TEXT_BASE=0x40200000 |
Heiko Thiery | 05a3d95 | 2022-01-31 17:30:45 +0100 | [diff] [blame] | 4 | CONFIG_SYS_MALLOC_LEN=0x600000 |
| 5 | CONFIG_SPL_GPIO=y |
| 6 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 7 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 8 | CONFIG_ENV_SIZE=0x4000 |
| 9 | CONFIG_ENV_OFFSET=0x300000 |
| 10 | CONFIG_SYS_I2C_MXC_I2C1=y |
| 11 | CONFIG_SYS_I2C_MXC_I2C2=y |
| 12 | CONFIG_SYS_I2C_MXC_I2C3=y |
| 13 | CONFIG_DM_GPIO=y |
| 14 | CONFIG_DEFAULT_DEVICE_TREE="imx8mq-kontron-pitx-imx8m" |
Heiko Thiery | 05a3d95 | 2022-01-31 17:30:45 +0100 | [diff] [blame] | 15 | CONFIG_TARGET_KONTRON_PITX_IMX8M=y |
Tom Rini | 9924ca1 | 2023-02-17 09:58:06 -0500 | [diff] [blame] | 16 | CONFIG_DM_RESET=y |
Tom Rini | 3d2b97c | 2023-05-29 10:43:26 -0400 | [diff] [blame] | 17 | CONFIG_SYS_MONITOR_LEN=524288 |
Heiko Thiery | 05a3d95 | 2022-01-31 17:30:45 +0100 | [diff] [blame] | 18 | CONFIG_SPL_MMC=y |
| 19 | CONFIG_SPL_SERIAL=y |
| 20 | CONFIG_SPL_DRIVERS_MISC=y |
Tom Rini | 9924ca1 | 2023-02-17 09:58:06 -0500 | [diff] [blame] | 21 | CONFIG_SPL_STACK=0x187ff0 |
Tom Rini | 27280b6 | 2024-11-12 13:45:12 -0600 | [diff] [blame] | 22 | CONFIG_SPL_TEXT_BASE=0x7E1000 |
Tom Rini | b9dc684 | 2024-04-22 17:24:09 -0600 | [diff] [blame] | 23 | CONFIG_SPL_HAS_BSS_LINKER_SECTION=y |
| 24 | CONFIG_SPL_BSS_START_ADDR=0x180000 |
| 25 | CONFIG_SPL_BSS_MAX_SIZE=0x2000 |
Tom Rini | c427a58 | 2024-10-08 09:18:32 -0600 | [diff] [blame] | 26 | CONFIG_SYS_BOOTM_LEN=0x2000000 |
| 27 | CONFIG_SYS_LOAD_ADDR=0x42000000 |
Heiko Thiery | 05a3d95 | 2022-01-31 17:30:45 +0100 | [diff] [blame] | 28 | CONFIG_SPL=y |
| 29 | CONFIG_IMX_BOOTAUX=y |
Tom Rini | 3a7c8a0 | 2022-03-11 07:12:48 -0500 | [diff] [blame] | 30 | CONFIG_REMAKE_ELF=y |
Tom Rini | c427a58 | 2024-10-08 09:18:32 -0600 | [diff] [blame] | 31 | CONFIG_EFI_SET_TIME=y |
| 32 | CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y |
| 33 | CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y |
Heiko Thiery | 05a3d95 | 2022-01-31 17:30:45 +0100 | [diff] [blame] | 34 | CONFIG_FIT=y |
| 35 | CONFIG_SPL_FIT_PRINT=y |
| 36 | CONFIG_SPL_LOAD_FIT=y |
Tom Rini | adb7a19 | 2023-03-27 13:39:17 -0400 | [diff] [blame] | 37 | CONFIG_DISTRO_DEFAULTS=y |
Tom Rini | 8d3a588 | 2023-10-02 13:58:20 -0400 | [diff] [blame] | 38 | CONFIG_OF_SYSTEM_SETUP=y |
Tom Rini | 914a8c0 | 2024-01-03 09:26:16 -0500 | [diff] [blame] | 39 | CONFIG_SYS_CBSIZE=256 |
| 40 | CONFIG_SYS_PBSIZE=276 |
Heiko Thiery | 05a3d95 | 2022-01-31 17:30:45 +0100 | [diff] [blame] | 41 | CONFIG_BOARD_EARLY_INIT_F=y |
| 42 | CONFIG_BOARD_LATE_INIT=y |
| 43 | CONFIG_MISC_INIT_R=y |
Tom Rini | abb0f52 | 2022-05-16 17:20:26 -0400 | [diff] [blame] | 44 | CONFIG_SPL_MAX_SIZE=0x1f000 |
Tom Rini | 8a14ac4 | 2022-05-26 13:13:21 -0400 | [diff] [blame] | 45 | # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set |
Simon Glass | 67e3fca | 2023-09-26 08:14:16 -0600 | [diff] [blame] | 46 | CONFIG_SPL_SYS_MALLOC=y |
| 47 | CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y |
| 48 | CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 |
| 49 | CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 |
Simon Glass | 1842283 | 2024-08-22 07:55:00 -0600 | [diff] [blame] | 50 | CONFIG_SPL_SYS_MMCSD_RAW_MODE=y |
Tom Rini | 3a7c8a0 | 2022-03-11 07:12:48 -0500 | [diff] [blame] | 51 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 |
Heiko Thiery | 05a3d95 | 2022-01-31 17:30:45 +0100 | [diff] [blame] | 52 | CONFIG_SPL_I2C=y |
| 53 | CONFIG_SPL_POWER=y |
| 54 | CONFIG_SPL_WATCHDOG=y |
| 55 | # CONFIG_BOOTM_NETBSD is not set |
| 56 | # CONFIG_CMD_EXPORTENV is not set |
| 57 | # CONFIG_CMD_IMPORTENV is not set |
| 58 | CONFIG_CMD_NVEDIT_EFI=y |
| 59 | # CONFIG_CMD_CRC32 is not set |
| 60 | CONFIG_CMD_DFU=y |
| 61 | CONFIG_CMD_FUSE=y |
| 62 | CONFIG_CMD_GPIO=y |
| 63 | CONFIG_CMD_GPT=y |
Heiko Thiery | 05a3d95 | 2022-01-31 17:30:45 +0100 | [diff] [blame] | 64 | CONFIG_CMD_I2C=y |
| 65 | CONFIG_CMD_MMC=y |
| 66 | CONFIG_CMD_USB=y |
| 67 | # CONFIG_CMD_MDIO is not set |
| 68 | CONFIG_CMD_CACHE=y |
| 69 | CONFIG_CMD_EFIDEBUG=y |
| 70 | CONFIG_CMD_RTC=y |
| 71 | CONFIG_CMD_TIME=y |
| 72 | CONFIG_CMD_REGULATOR=y |
| 73 | CONFIG_CMD_HASH=y |
| 74 | CONFIG_CMD_EXT4_WRITE=y |
| 75 | CONFIG_OF_CONTROL=y |
| 76 | CONFIG_ENV_OVERWRITE=y |
| 77 | CONFIG_ENV_IS_IN_MMC=y |
| 78 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
Tom Rini | fe58675 | 2022-03-11 09:12:07 -0500 | [diff] [blame] | 79 | CONFIG_USE_ETHPRIME=y |
| 80 | CONFIG_ETHPRIME="FEC" |
Heiko Thiery | 05a3d95 | 2022-01-31 17:30:45 +0100 | [diff] [blame] | 81 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 |
| 82 | CONFIG_DFU_MMC=y |
| 83 | CONFIG_MXC_GPIO=y |
| 84 | CONFIG_DM_I2C=y |
| 85 | CONFIG_SPL_SYS_I2C_LEGACY=y |
| 86 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 87 | CONFIG_FSL_USDHC=y |
| 88 | CONFIG_PHYLIB=y |
Marek Vasut | e4d70fd | 2024-05-31 18:47:17 +0200 | [diff] [blame] | 89 | CONFIG_PHY_ANEG_TIMEOUT=20000 |
Heiko Thiery | 05a3d95 | 2022-01-31 17:30:45 +0100 | [diff] [blame] | 90 | CONFIG_PHY_TI=y |
Heiko Thiery | 05a3d95 | 2022-01-31 17:30:45 +0100 | [diff] [blame] | 91 | CONFIG_PHY_GIGE=y |
| 92 | CONFIG_FEC_MXC=y |
| 93 | CONFIG_MII=y |
| 94 | CONFIG_PHY=y |
| 95 | CONFIG_PHY_IMX8MQ_USB=y |
| 96 | CONFIG_PINCTRL=y |
| 97 | CONFIG_PINCTRL_IMX8M=y |
| 98 | CONFIG_SPL_POWER_LEGACY=y |
| 99 | CONFIG_POWER_DOMAIN=y |
| 100 | CONFIG_IMX8M_POWER_DOMAIN=y |
Tom Rini | db9d925 | 2022-11-19 18:45:15 -0500 | [diff] [blame] | 101 | CONFIG_POWER_PFUZE100=y |
Heiko Thiery | 05a3d95 | 2022-01-31 17:30:45 +0100 | [diff] [blame] | 102 | CONFIG_DM_REGULATOR=y |
| 103 | CONFIG_DM_REGULATOR_FIXED=y |
| 104 | CONFIG_DM_REGULATOR_GPIO=y |
| 105 | CONFIG_SPL_POWER_I2C=y |
Heiko Thiery | 05a3d95 | 2022-01-31 17:30:45 +0100 | [diff] [blame] | 106 | CONFIG_DM_RTC=y |
| 107 | CONFIG_RTC_RV8803=y |
| 108 | CONFIG_DM_SERIAL=y |
| 109 | CONFIG_MXC_UART=y |
| 110 | CONFIG_DM_THERMAL=y |
| 111 | CONFIG_USB=y |
| 112 | CONFIG_USB_XHCI_HCD=y |
| 113 | CONFIG_USB_XHCI_DWC3=y |
| 114 | CONFIG_USB_DWC3=y |
Tom Rini | 914a8c0 | 2024-01-03 09:26:16 -0500 | [diff] [blame] | 115 | # CONFIG_RANDOM_UUID is not set |