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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk38635852002-08-27 05:55:31 +00002/*
3 * (C) Copyright 2000
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenk38635852002-08-27 05:55:31 +00005 */
6
7/*
8 * Cache support: switch on or off, get status
9 */
wdenk38635852002-08-27 05:55:31 +000010#include <command.h>
Simon Glass1d91ba72019-11-14 12:57:37 -070011#include <cpu_func.h>
Matthew McClintocka14695e2011-05-24 10:09:05 +000012#include <linux/compiler.h>
wdenk38635852002-08-27 05:55:31 +000013
Matthew McClintocka14695e2011-05-24 10:09:05 +000014static int parse_argv(const char *);
15
Simon Glassed38aef2020-05-10 11:40:03 -060016static int do_icache(struct cmd_tbl *cmdtp, int flag, int argc,
17 char *const argv[])
wdenk38635852002-08-27 05:55:31 +000018{
19 switch (argc) {
Eric Perie86b7ba52019-07-13 14:54:58 -040020 case 2: /* on / off / flush */
Matthew McClintocka14695e2011-05-24 10:09:05 +000021 switch (parse_argv(argv[1])) {
Joe Hershberger3745b8c2012-10-03 10:56:16 +000022 case 0:
23 icache_disable();
wdenk38635852002-08-27 05:55:31 +000024 break;
Joe Hershberger3745b8c2012-10-03 10:56:16 +000025 case 1:
26 icache_enable();
wdenk38635852002-08-27 05:55:31 +000027 break;
Joe Hershberger3745b8c2012-10-03 10:56:16 +000028 case 2:
29 invalidate_icache_all();
Matthew McClintocka14695e2011-05-24 10:09:05 +000030 break;
Eric Perie86b7ba52019-07-13 14:54:58 -040031 default:
32 return CMD_RET_USAGE;
wdenk38635852002-08-27 05:55:31 +000033 }
Joe Hershberger8cab1562012-10-03 10:56:17 +000034 break;
wdenk38635852002-08-27 05:55:31 +000035 case 1: /* get status */
Joe Hershberger3745b8c2012-10-03 10:56:16 +000036 printf("Instruction Cache is %s\n",
wdenk38635852002-08-27 05:55:31 +000037 icache_status() ? "ON" : "OFF");
38 return 0;
39 default:
Simon Glassa06dfc72011-12-10 08:44:01 +000040 return CMD_RET_USAGE;
wdenk38635852002-08-27 05:55:31 +000041 }
42 return 0;
43}
44
Simon Glassed38aef2020-05-10 11:40:03 -060045static int do_dcache(struct cmd_tbl *cmdtp, int flag, int argc,
46 char *const argv[])
wdenk38635852002-08-27 05:55:31 +000047{
48 switch (argc) {
Eric Perie86b7ba52019-07-13 14:54:58 -040049 case 2: /* on / off / flush */
Matthew McClintocka14695e2011-05-24 10:09:05 +000050 switch (parse_argv(argv[1])) {
Joe Hershberger3745b8c2012-10-03 10:56:16 +000051 case 0:
52 dcache_disable();
wdenk38635852002-08-27 05:55:31 +000053 break;
Joe Hershberger3745b8c2012-10-03 10:56:16 +000054 case 1:
55 dcache_enable();
Tom Rinif7732322024-06-19 15:27:59 -060056#ifdef CONFIG_SYS_NONCACHED_MEMORY
Patrice Chotarde2eb7212020-04-28 11:38:03 +020057 noncached_set_region();
Tom Rinif7732322024-06-19 15:27:59 -060058#endif
wdenk38635852002-08-27 05:55:31 +000059 break;
Joe Hershberger3745b8c2012-10-03 10:56:16 +000060 case 2:
61 flush_dcache_all();
Matthew McClintocka14695e2011-05-24 10:09:05 +000062 break;
Eric Perie86b7ba52019-07-13 14:54:58 -040063 default:
64 return CMD_RET_USAGE;
wdenk38635852002-08-27 05:55:31 +000065 }
Joe Hershberger3745b8c2012-10-03 10:56:16 +000066 break;
wdenk38635852002-08-27 05:55:31 +000067 case 1: /* get status */
Joe Hershberger3745b8c2012-10-03 10:56:16 +000068 printf("Data (writethrough) Cache is %s\n",
wdenk38635852002-08-27 05:55:31 +000069 dcache_status() ? "ON" : "OFF");
70 return 0;
71 default:
Simon Glassa06dfc72011-12-10 08:44:01 +000072 return CMD_RET_USAGE;
wdenk38635852002-08-27 05:55:31 +000073 }
74 return 0;
wdenk38635852002-08-27 05:55:31 +000075}
76
Matthew McClintocka14695e2011-05-24 10:09:05 +000077static int parse_argv(const char *s)
wdenk38635852002-08-27 05:55:31 +000078{
Joe Hershberger3745b8c2012-10-03 10:56:16 +000079 if (strcmp(s, "flush") == 0)
80 return 2;
81 else if (strcmp(s, "on") == 0)
82 return 1;
83 else if (strcmp(s, "off") == 0)
84 return 0;
85
86 return -1;
wdenk38635852002-08-27 05:55:31 +000087}
88
wdenkf287a242003-07-01 21:06:45 +000089U_BOOT_CMD(
90 icache, 2, 1, do_icache,
Peter Tyserdfb72b82009-01-27 18:03:12 -060091 "enable or disable instruction cache",
Matthew McClintocka14695e2011-05-24 10:09:05 +000092 "[on, off, flush]\n"
93 " - enable, disable, or flush instruction cache"
wdenk57b2d802003-06-27 21:31:46 +000094);
95
wdenkf287a242003-07-01 21:06:45 +000096U_BOOT_CMD(
97 dcache, 2, 1, do_dcache,
Peter Tyserdfb72b82009-01-27 18:03:12 -060098 "enable or disable data cache",
Matthew McClintocka14695e2011-05-24 10:09:05 +000099 "[on, off, flush]\n"
100 " - enable, disable, or flush data (writethrough) cache"
wdenk57b2d802003-06-27 21:31:46 +0000101);