| Suneel Garapati | cd53028 | 2019-10-19 18:32:33 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 |
| 2 | * |
| 3 | * Copyright (C) 2018 Marvell International Ltd. |
| 4 | * |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
| 8 | #ifndef __BOARD_H__ |
| 9 | #define __BOARD_H__ |
| 10 | |
| 11 | #include <asm/arch/soc.h> |
| 12 | |
| 13 | #define MAX_LMAC_PER_BGX 4 |
| 14 | #define LMAC_CNT MAX_LMAC_PER_BGX |
| 15 | |
| 16 | #if defined(CONFIG_TARGET_OCTEONTX_81XX) |
| 17 | |
| 18 | /** Maximum number of BGX interfaces per CPU node */ |
| 19 | #define MAX_BGX_PER_NODE 3 |
| 20 | #define OCTEONTX_XCV /* RGMII Interface */ |
| 21 | |
| 22 | #elif defined(CONFIG_TARGET_OCTEONTX_83XX) |
| 23 | |
| 24 | /** Maximum number of BGX interfaces per CPU node */ |
| 25 | #define MAX_BGX_PER_NODE 4 |
| 26 | |
| 27 | #endif |
| 28 | |
| 29 | /** Reg offsets */ |
| 30 | #define RST_BOOT 0x87E006001600ULL |
| 31 | |
| 32 | /** Structure definitions */ |
| 33 | |
| 34 | /** |
| 35 | * Register (RSL) rst_boot |
| 36 | * |
| 37 | * RST Boot Register This register is not accessible through ROM scripts; |
| 38 | * see SCR_WRITE32_S[ADDR]. |
| 39 | */ |
| 40 | union rst_boot { |
| 41 | u64 u; |
| 42 | struct rst_boot_s { |
| 43 | u64 rboot_pin : 1; |
| 44 | u64 rboot : 1; |
| 45 | u64 reserved_2_32 : 31; |
| 46 | u64 pnr_mul : 6; |
| 47 | u64 reserved_39 : 1; |
| 48 | u64 c_mul : 7; |
| 49 | u64 reserved_47_52 : 6; |
| 50 | u64 gpio_ejtag : 1; |
| 51 | u64 mcp_jtagdis : 1; |
| 52 | u64 dis_scan : 1; |
| 53 | u64 dis_huk : 1; |
| 54 | u64 vrm_err : 1; |
| 55 | u64 jt_tstmode : 1; |
| 56 | u64 ckill_ppdis : 1; |
| 57 | u64 trusted_mode : 1; |
| 58 | u64 reserved_61_62 : 2; |
| 59 | u64 chipkill : 1; |
| 60 | } s; |
| 61 | struct rst_boot_cn81xx { |
| 62 | u64 rboot_pin : 1; |
| 63 | u64 rboot : 1; |
| 64 | u64 lboot : 10; |
| 65 | u64 lboot_ext23 : 6; |
| 66 | u64 lboot_ext45 : 6; |
| 67 | u64 lboot_jtg : 1; |
| 68 | u64 lboot_ckill : 1; |
| 69 | u64 reserved_26_29 : 4; |
| 70 | u64 lboot_oci : 3; |
| 71 | u64 pnr_mul : 6; |
| 72 | u64 reserved_39 : 1; |
| 73 | u64 c_mul : 7; |
| 74 | u64 reserved_47_54 : 8; |
| 75 | u64 dis_scan : 1; |
| 76 | u64 dis_huk : 1; |
| 77 | u64 vrm_err : 1; |
| 78 | u64 jt_tstmode : 1; |
| 79 | u64 ckill_ppdis : 1; |
| 80 | u64 trusted_mode : 1; |
| 81 | u64 ejtagdis : 1; |
| 82 | u64 jtcsrdis : 1; |
| 83 | u64 chipkill : 1; |
| 84 | } cn81xx; |
| 85 | struct rst_boot_cn83xx { |
| 86 | u64 rboot_pin : 1; |
| 87 | u64 rboot : 1; |
| 88 | u64 lboot : 10; |
| 89 | u64 lboot_ext23 : 6; |
| 90 | u64 lboot_ext45 : 6; |
| 91 | u64 lboot_jtg : 1; |
| 92 | u64 lboot_ckill : 1; |
| 93 | u64 lboot_pf_flr : 4; |
| 94 | u64 lboot_oci : 3; |
| 95 | u64 pnr_mul : 6; |
| 96 | u64 reserved_39 : 1; |
| 97 | u64 c_mul : 7; |
| 98 | u64 reserved_47_54 : 8; |
| 99 | u64 dis_scan : 1; |
| 100 | u64 dis_huk : 1; |
| 101 | u64 vrm_err : 1; |
| 102 | u64 jt_tstmode : 1; |
| 103 | u64 ckill_ppdis : 1; |
| 104 | u64 trusted_mode : 1; |
| 105 | u64 ejtagdis : 1; |
| 106 | u64 jtcsrdis : 1; |
| 107 | u64 chipkill : 1; |
| 108 | } cn83xx; |
| 109 | }; |
| 110 | |
| 111 | extern unsigned long fdt_base_addr; |
| 112 | |
| 113 | /** Function definitions */ |
| 114 | void mem_map_fill(void); |
| 115 | int octeontx_board_has_pmp(void); |
| 116 | const char *fdt_get_board_model(void); |
| 117 | const char *fdt_get_board_serial(void); |
| 118 | const char *fdt_get_board_revision(void); |
| 119 | void fdt_parse_phy_info(void); |
| 120 | void fdt_board_get_ethaddr(int bgx, int lmac, unsigned char *eth); |
| 121 | void bgx_set_board_info(int bgx_id, int *mdio_bus, int *phy_addr, |
| 122 | bool *autoneg_dis, bool *lmac_reg, bool *lmac_enable); |
| 123 | #endif /* __BOARD_H__ */ |