blob: f661615c1b91efada8ab7e02dff4d36043dd71ac [file] [log] [blame]
Joseph Chenc63f2fc2021-06-02 15:58:24 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd.
4 */
5
Tom Riniabb9a042024-05-18 20:20:43 -06006#include <common.h>
Joseph Chenc63f2fc2021-06-02 15:58:24 +08007#include <dm.h>
8#include <ram.h>
9#include <syscon.h>
10#include <asm/arch-rockchip/clock.h>
11#include <asm/arch-rockchip/grf_rk3568.h>
12#include <asm/arch-rockchip/sdram.h>
13
14struct dram_info {
15 struct ram_info info;
16 struct rk3568_pmugrf *pmugrf;
17};
18
19static int rk3568_dmc_probe(struct udevice *dev)
20{
21 struct dram_info *priv = dev_get_priv(dev);
22
23 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
Tom Rinibb4dd962022-11-16 13:10:37 -050024 priv->info.base = CFG_SYS_SDRAM_BASE;
Joseph Chenc63f2fc2021-06-02 15:58:24 +080025 priv->info.size =
26 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->pmu_os_reg2);
27
28 return 0;
29}
30
31static int rk3568_dmc_get_info(struct udevice *dev, struct ram_info *info)
32{
33 struct dram_info *priv = dev_get_priv(dev);
34
35 *info = priv->info;
36
37 return 0;
38}
39
40static struct ram_ops rk3568_dmc_ops = {
41 .get_info = rk3568_dmc_get_info,
42};
43
44static const struct udevice_id rk3568_dmc_ids[] = {
45 { .compatible = "rockchip,rk3568-dmc" },
46 { }
47};
48
49U_BOOT_DRIVER(dmc_rk3568) = {
50 .name = "rockchip_rk3568_dmc",
51 .id = UCLASS_RAM,
52 .of_match = rk3568_dmc_ids,
53 .ops = &rk3568_dmc_ops,
54 .probe = rk3568_dmc_probe,
55 .priv_auto = sizeof(struct dram_info),
56};