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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ye Lib3d60d52016-02-01 10:41:32 +08002/*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 *
5 * Author: Ye Li <ye.li@nxp.com>
Ye Lib3d60d52016-02-01 10:41:32 +08006 */
7
Simon Glassa7b51302019-11-14 12:57:46 -07008#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -06009#include <net.h>
Ye Lib3d60d52016-02-01 10:41:32 +080010#include <asm/arch/clock.h>
11#include <asm/arch/crm_regs.h>
12#include <asm/arch/iomux.h>
13#include <asm/arch/imx-regs.h>
14#include <asm/arch/mx6-pins.h>
15#include <asm/arch/sys_proto.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060016#include <asm/global_data.h>
Ye Lib3d60d52016-02-01 10:41:32 +080017#include <asm/gpio.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020018#include <asm/mach-imx/iomux-v3.h>
19#include <asm/mach-imx/boot_mode.h>
Ye Lib3d60d52016-02-01 10:41:32 +080020#include <asm/io.h>
Simon Glassdbd79542020-05-10 11:40:11 -060021#include <linux/delay.h>
Ye Lib3d60d52016-02-01 10:41:32 +080022#include <linux/sizes.h>
Tom Riniabb9a042024-05-18 20:20:43 -060023#include <common.h>
Yangbo Lu73340382019-06-21 11:42:28 +080024#include <fsl_esdhc_imx.h>
Ye Lib3d60d52016-02-01 10:41:32 +080025#include <miiphy.h>
26#include <netdev.h>
27#include <power/pmic.h>
28#include <power/pfuze100_pmic.h>
29#include "../common/pfuze.h"
30#include <usb.h>
Mateusz Kulikowski3add69e2016-03-31 23:12:23 +020031#include <usb/ehci-ci.h>
Ye Lib3d60d52016-02-01 10:41:32 +080032#include <pca953x.h>
33
34DECLARE_GLOBAL_DATA_PTR;
35
Ye Lib3d60d52016-02-01 10:41:32 +080036#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
37 PAD_CTL_SPEED_HIGH | \
38 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
39
40#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
41 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
42
43#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
44 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
45
Ye Lib3d60d52016-02-01 10:41:32 +080046#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
47#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
48 PAD_CTL_SRE_FAST)
49#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
50
Ye Lib3d60d52016-02-01 10:41:32 +080051int dram_init(void)
52{
Vanessa Maegima610a36d2016-06-09 15:28:32 -030053 gd->ram_size = imx_ddr_size();
Ye Lib3d60d52016-02-01 10:41:32 +080054
55 return 0;
56}
57
Ye Lib3d60d52016-02-01 10:41:32 +080058static iomux_v3_cfg_t const fec2_pads[] = {
59 MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
60 MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
61 MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
62 MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
63 MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
64 MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
65 MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
66 MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
67 MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
68 MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
69 MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
73};
74
Ye Lib3d60d52016-02-01 10:41:32 +080075static int setup_fec(void)
76{
77 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
78
79 /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
80 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
81
82 return enable_fec_anatop_clock(1, ENET_125MHZ);
83}
84
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090085int board_eth_init(struct bd_info *bis)
Ye Lib3d60d52016-02-01 10:41:32 +080086{
87 int ret;
88
89 imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
90 setup_fec();
91
92 ret = fecmxc_initialize_multi(bis, 1,
Tom Rini4e3c8a62022-12-04 10:03:53 -050093 CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
Ye Lib3d60d52016-02-01 10:41:32 +080094 if (ret)
95 printf("FEC%d MXC: %s:failed\n", 1, __func__);
96
97 return ret;
98}
99
100int board_phy_config(struct phy_device *phydev)
101{
102 /*
103 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
104 * Phy control debug reg 0
105 */
106 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
107 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
108
109 /* rgmii tx clock delay enable */
110 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
111 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
112
113 if (phydev->drv->config)
114 phydev->drv->config(phydev);
115
116 return 0;
117}
118
Ye Lib3d60d52016-02-01 10:41:32 +0800119int power_init_board(void)
120{
Peng Fan9bd7bd52016-11-28 17:49:50 +0800121 struct udevice *dev;
122 int ret;
123 u32 dev_id, rev_id, i;
124 u32 switch_num = 6;
125 u32 offset = PFUZE100_SW1CMODE;
126
127 ret = pmic_get("pfuze100", &dev);
128 if (ret == -ENODEV)
129 return 0;
130
131 if (ret != 0)
132 return ret;
133
134 dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
135 rev_id = pmic_reg_read(dev, PFUZE100_REVID);
136 printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
Ye Lib3d60d52016-02-01 10:41:32 +0800137
Peng Fan9bd7bd52016-11-28 17:49:50 +0800138
139 /* Init mode to APS_PFM */
140 pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
141
142 for (i = 0; i < switch_num - 1; i++)
143 pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
144
145 /* set SW1AB staby volatage 0.975V */
146 pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
147
148 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
149 pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
150
151 /* set SW1C staby volatage 1.10V */
152 pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20);
153
154 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
155 pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
Ye Lib3d60d52016-02-01 10:41:32 +0800156
157 return 0;
158}
159
160#ifdef CONFIG_USB_EHCI_MX6
161#define USB_OTHERREGS_OFFSET 0x800
162#define UCTRL_PWR_POL (1 << 9)
163
164static iomux_v3_cfg_t const usb_otg_pads[] = {
165 /* OGT1 */
166 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
167 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
168 /* OTG2 */
169 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
170};
171
172static void setup_usb(void)
173{
174 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
175 ARRAY_SIZE(usb_otg_pads));
176}
177
178int board_usb_phy_mode(int port)
179{
180 if (port == 1)
181 return USB_INIT_HOST;
182 else
183 return usb_phy_mode(port);
184}
185
186int board_ehci_hcd_init(int port)
187{
188 u32 *usbnc_usb_ctrl;
189
190 if (port > 1)
191 return -EINVAL;
192
193 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
194 port * 4);
195
196 /* Set Power polarity */
197 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
198
199 return 0;
200}
201#endif
202
203int board_early_init_f(void)
204{
Ye Lib3d60d52016-02-01 10:41:32 +0800205 return 0;
206}
207
Ye Lib3d60d52016-02-01 10:41:32 +0800208#ifdef CONFIG_FSL_QSPI
Ye Lib3d60d52016-02-01 10:41:32 +0800209int board_qspi_init(void)
210{
Ye Lib3d60d52016-02-01 10:41:32 +0800211 /* Set the clock */
212 enable_qspi_clk(0);
213
214 return 0;
215}
216#endif
217
218#ifdef CONFIG_NAND_MXS
219iomux_v3_cfg_t gpmi_pads[] = {
220 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
221 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
222 MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
223 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
224 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
225 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
226 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
227 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
228 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
229 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
230 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
231 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
232 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
233 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
234 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
235};
236
237static void setup_gpmi_nand(void)
238{
239 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
240
241 /* config gpmi nand iomux */
242 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
243
244 setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
245 MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
246 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));
247
248 /* enable apbh clock gating */
249 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
250}
251#endif
252
253int board_init(void)
254{
Peng Fan9bd7bd52016-11-28 17:49:50 +0800255 struct gpio_desc desc;
256 int ret;
257
Ye Lib3d60d52016-02-01 10:41:32 +0800258 /* Address of boot parameters */
259 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
260
Peng Fan9bd7bd52016-11-28 17:49:50 +0800261 ret = dm_gpio_lookup_name("gpio@30_4", &desc);
262 if (ret)
263 return ret;
Ye Lib3d60d52016-02-01 10:41:32 +0800264
Peng Fan9bd7bd52016-11-28 17:49:50 +0800265 ret = dm_gpio_request(&desc, "cpu_per_rst_b");
266 if (ret)
267 return ret;
Ye Lib3d60d52016-02-01 10:41:32 +0800268 /* Reset CPU_PER_RST_B signal for enet phy and PCIE */
Peng Fan9bd7bd52016-11-28 17:49:50 +0800269 dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
Ye Lib3d60d52016-02-01 10:41:32 +0800270 udelay(500);
Peng Fan9bd7bd52016-11-28 17:49:50 +0800271 dm_gpio_set_value(&desc, 1);
272
273 ret = dm_gpio_lookup_name("gpio@32_2", &desc);
274 if (ret)
275 return ret;
Ye Lib3d60d52016-02-01 10:41:32 +0800276
Peng Fan9bd7bd52016-11-28 17:49:50 +0800277 ret = dm_gpio_request(&desc, "steer_enet");
278 if (ret)
279 return ret;
280
281 dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
282 udelay(500);
Ye Lib3d60d52016-02-01 10:41:32 +0800283 /* Set steering signal to L for selecting B0 */
Peng Fan9bd7bd52016-11-28 17:49:50 +0800284 dm_gpio_set_value(&desc, 0);
Ye Lib3d60d52016-02-01 10:41:32 +0800285
286#ifdef CONFIG_USB_EHCI_MX6
287 setup_usb();
288#endif
289
290#ifdef CONFIG_FSL_QSPI
291 board_qspi_init();
292#endif
293
294#ifdef CONFIG_NAND_MXS
295 setup_gpmi_nand();
296#endif
297
298 return 0;
299}
300
301#ifdef CONFIG_CMD_BMODE
302static const struct boot_mode board_boot_modes[] = {
303 {"sda", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
304 {"sdb", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
305 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
306 {"nand", MAKE_CFGVAL(0x82, 0x00, 0x00, 0x00)},
307 {NULL, 0},
308};
309#endif
310
311int board_late_init(void)
312{
313#ifdef CONFIG_CMD_BMODE
314 add_board_boot_modes(board_boot_modes);
315#endif
316
317 return 0;
318}
319
320int checkboard(void)
321{
322 puts("Board: MX6SX SABRE AUTO\n");
323
324 return 0;
325}