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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk591dda52002-11-18 00:14:45 +00002/*
Wolfgang Denkf710efd2010-07-24 20:22:02 +02003 * (C) Copyright 2002-2010
wdenk591dda52002-11-18 00:14:45 +00004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenk591dda52002-11-18 00:14:45 +00005 */
6
7#ifndef __ASM_GBL_DATA_H
8#define __ASM_GBL_DATA_H
Simon Glass3ac47d72012-12-13 20:48:30 +00009
10#ifndef __ASSEMBLY__
11
Tom Rini10e6a372023-12-14 13:16:52 -050012#include <linux/types.h>
Simon Glass9909bf32015-08-10 20:44:31 -060013#include <asm/processor.h>
Simon Glassc3d0c232019-12-06 21:42:05 -070014#include <asm/mrccache.h>
Simon Glass9909bf32015-08-10 20:44:31 -060015
Simon Glass30580fc2014-11-12 22:42:23 -070016enum pei_boot_mode_t {
17 PEI_BOOT_NONE = 0,
18 PEI_BOOT_SOFT_RESET,
19 PEI_BOOT_RESUME,
20
21};
22
Simon Glassd21f34e2016-03-11 22:07:26 -070023struct dimm_info {
24 uint32_t dimm_size;
25 uint16_t ddr_type;
26 uint16_t ddr_frequency;
27 uint8_t rank_per_dimm;
28 uint8_t channel_num;
29 uint8_t dimm_num;
30 uint8_t bank_locator;
31 /* The 5th byte is '\0' for the end of string */
32 uint8_t serial[5];
33 /* The 19th byte is '\0' for the end of string */
34 uint8_t module_part_number[19];
35 uint16_t mod_id;
36 uint8_t mod_type;
37 uint8_t bus_width;
38} __packed;
39
40struct pei_memory_info {
41 uint8_t dimm_cnt;
42 /* Maximum num of dimm is 8 */
43 struct dimm_info dimm[8];
44} __packed;
45
Simon Glass268eefd2014-11-12 22:42:28 -070046struct memory_area {
47 uint64_t start;
48 uint64_t size;
49};
50
51struct memory_info {
52 int num_areas;
53 uint64_t total_memory;
54 uint64_t total_32bit_memory;
55 struct memory_area area[CONFIG_NR_DRAM_BANKS];
56};
57
Simon Glass7bf5b9e2015-01-01 16:18:07 -070058#define MAX_MTRR_REQUESTS 8
59
60/**
61 * A request for a memory region to be set up in a particular way. These
62 * requests are processed before board_init_r() is called. They are generally
63 * optional and can be ignored with some performance impact.
64 */
65struct mtrr_request {
66 int type; /* MTRR_TYPE_... */
67 uint64_t start;
68 uint64_t size;
69};
70
Simon Glass91efff52019-12-06 21:42:07 -070071/**
72 * struct mrc_output - holds the MRC data
73 *
74 * @buf: MRC training data to save for the next boot. This is set to point to
75 * the raw data after SDRAM init is complete. Then mrccache_setup()
76 * turns it into a proper cache record with a checksum
77 * @len: Length of @buf
78 * @cache: Resulting cache record
79 */
80struct mrc_output {
81 char *buf;
82 uint len;
83 struct mrc_data_container *cache;
84};
85
Simon Glass3ac47d72012-12-13 20:48:30 +000086/* Architecture-specific global data */
87struct arch_global_data {
Simon Glass9909bf32015-08-10 20:44:31 -060088 u64 gdt[X86_GDT_NUM_ENTRIES] __aligned(16);
Bin Meng47eac042015-01-22 11:29:40 +080089 struct global_data *gd_addr; /* Location of Global Data */
90 uint8_t x86; /* CPU family */
91 uint8_t x86_vendor; /* CPU vendor */
92 uint8_t x86_model;
93 uint8_t x86_mask;
Bin Meng035c1d22014-11-09 22:18:56 +080094 uint32_t x86_device;
Simon Glass6fa6e4a2013-02-28 19:26:12 +000095 uint64_t tsc_base; /* Initial value returned by rdtsc() */
Simon Glassed10a4f2019-10-20 21:37:47 -060096 bool tsc_inited; /* true if tsc is ready for use */
Simon Glass471919d2017-09-05 19:49:46 -060097 unsigned long clock_rate; /* Clock rate of timer in Hz */
Simon Glass347c05b2013-02-28 19:26:15 +000098 void *new_fdt; /* Relocated FDT */
Simon Glass1f4476c2014-11-06 13:20:10 -070099 uint32_t bist; /* Built-in self test value */
Simon Glass30580fc2014-11-12 22:42:23 -0700100 enum pei_boot_mode_t pei_boot_mode;
Simon Glass60af0172014-11-12 22:42:24 -0700101 const struct pch_gpio_map *gpio_map; /* board GPIO map */
Simon Glass268eefd2014-11-12 22:42:28 -0700102 struct memory_info meminfo; /* Memory information */
Simon Glassd21f34e2016-03-11 22:07:26 -0700103 struct pei_memory_info pei_meminfo; /* PEI memory information */
Park, Aiden6e3cc362019-08-03 08:30:12 +0000104#ifdef CONFIG_USE_HOB
Bin Meng47eac042015-01-22 11:29:40 +0800105 void *hob_list; /* FSP HOB list */
Bin Meng005f0af2014-12-12 21:05:31 +0800106#endif
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700107 struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS];
108 int mtrr_req_count;
Bin Meng47eac042015-01-22 11:29:40 +0800109 int has_mtrr;
Simon Glass91efff52019-12-06 21:42:07 -0700110 /* MRC training data */
111 struct mrc_output mrc[MRC_TYPE_COUNT];
Simon Glassf95ad8c2015-08-04 12:33:57 -0600112 ulong table; /* Table pointer from previous loader */
Simon Glass37e706d2017-01-16 07:04:17 -0700113 int turbo_state; /* Current turbo state */
Simon Glassf64d6f72017-01-16 07:04:16 -0700114 struct irq_routing_table *pirq_routing_table;
Simon Glassf5bdce22019-12-06 21:41:41 -0700115 int dw_i2c_num_cards; /* Used by designware i2c driver */
Bin Meng322ec3e2016-05-11 07:44:59 -0700116#ifdef CONFIG_SEABIOS
117 u32 high_table_ptr;
118 u32 high_table_limit;
119#endif
Bin Meng2ee5b852017-04-21 07:24:33 -0700120 int prev_sleep_state; /* Previous sleep state ACPI_S0/1../5 */
Bin Meng353f5cb2017-04-21 07:24:47 -0700121 ulong backup_mem; /* Backup memory address for S3 */
Simon Glass26561da2019-12-06 21:42:21 -0700122#ifdef CONFIG_FSP_VERSION2
123 struct fsp_header *fsp_s_hdr; /* Pointer to FSP-S header */
124#endif
Simon Glassd89f1932020-07-16 21:22:30 -0600125 void *itss_priv; /* Private ITSS data pointer */
Simon Glassfb8736d2020-07-16 21:22:34 -0600126 ulong coreboot_table; /* Address of coreboot table */
Simon Glass66ca25c2023-07-15 21:39:10 -0600127 ulong table_start; /* Start address of x86 tables */
128 ulong table_end; /* End address of x86 tables */
129 ulong table_start_high; /* Start address of high x86 tables */
130 ulong table_end_high; /* End address of high x86 tables */
Simon Glass9b388102023-09-19 21:00:15 -0600131 ulong smbios_start; /* Start address of SMBIOS table */
Simon Glass3ac47d72012-12-13 20:48:30 +0000132};
133
Graeme Russ3c28f482011-09-01 00:48:27 +0000134#endif
wdenk591dda52002-11-18 00:14:45 +0000135
Simon Glassd3887632012-12-13 20:49:27 +0000136#include <asm-generic/global_data.h>
137
138#ifndef __ASSEMBLY__
Simon Glass590aef72017-01-16 07:03:59 -0700139# if defined(CONFIG_EFI_APP) || CONFIG_IS_ENABLED(X86_64)
Simon Glass7f65c092015-07-31 09:31:35 -0600140
Simon Glass590aef72017-01-16 07:03:59 -0700141/* TODO(sjg@chromium.org): Consider using a fixed register for gd on x86_64 */
Simon Glass7f65c092015-07-31 09:31:35 -0600142#define gd global_data_ptr
143
144#define DECLARE_GLOBAL_DATA_PTR extern struct global_data *global_data_ptr
145# else
Simon Glass56da76d2022-12-21 16:08:15 -0700146static inline notrace gd_t *get_fs_gd_ptr(void)
Graeme Russ35368962011-12-31 22:58:15 +1100147{
148 gd_t *gd_ptr;
149
Simon Glass590aef72017-01-16 07:03:59 -0700150#if CONFIG_IS_ENABLED(X86_64)
151 asm volatile("fs mov 0, %0\n" : "=r" (gd_ptr));
152#else
Graeme Russ35368962011-12-31 22:58:15 +1100153 asm volatile("fs movl 0, %0\n" : "=r" (gd_ptr));
Simon Glass590aef72017-01-16 07:03:59 -0700154#endif
Graeme Russ35368962011-12-31 22:58:15 +1100155
156 return gd_ptr;
157}
158
159#define gd get_fs_gd_ptr()
Graeme Russ5fb91cc2010-10-07 20:03:29 +1100160
Simon Glass5d18dc92015-07-31 09:31:28 -0600161#define DECLARE_GLOBAL_DATA_PTR
Simon Glass7f65c092015-07-31 09:31:35 -0600162# endif
Simon Glass5d18dc92015-07-31 09:31:28 -0600163
Graeme Russ5fb91cc2010-10-07 20:03:29 +1100164#endif
165
wdenk591dda52002-11-18 00:14:45 +0000166#endif /* __ASM_GBL_DATA_H */