wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003 |
| 3 | * AT91RM9200 definitions |
| 4 | * Author : ATMEL AT91 application group |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 24 | |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 25 | #ifndef AT91RM9200_H |
| 26 | #define AT91RM9200_H |
| 27 | |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 28 | typedef volatile unsigned int AT91_REG; /* Hardware register definition */ |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 29 | |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 30 | /*****************************************************************************/ |
| 31 | /* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ |
| 32 | /*****************************************************************************/ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 33 | typedef struct _AT91S_TC |
| 34 | { |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 35 | AT91_REG TC_CCR; /* Channel Control Register */ |
| 36 | AT91_REG TC_CMR; /* Channel Mode Register */ |
| 37 | AT91_REG Reserved0[2]; /* */ |
| 38 | AT91_REG TC_CV; /* Counter Value */ |
| 39 | AT91_REG TC_RA; /* Register A */ |
| 40 | AT91_REG TC_RB; /* Register B */ |
| 41 | AT91_REG TC_RC; /* Register C */ |
| 42 | AT91_REG TC_SR; /* Status Register */ |
| 43 | AT91_REG TC_IER; /* Interrupt Enable Register */ |
| 44 | AT91_REG TC_IDR; /* Interrupt Disable Register */ |
| 45 | AT91_REG TC_IMR; /* Interrupt Mask Register */ |
Wolfgang Denk | bc650fa | 2005-10-05 01:51:29 +0200 | [diff] [blame] | 46 | } AT91S_TC, *AT91PS_TC; |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 47 | |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 48 | #define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */ |
| 49 | #define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */ |
| 50 | #define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */ |
| 51 | #define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */ |
| 52 | #define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK*/ |
| 53 | #define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */ |
| 54 | #define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */ |
| 55 | #define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */ |
| 56 | #define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */ |
| 57 | #define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */ |
| 58 | #define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */ |
| 59 | #define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */ |
| 60 | #define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */ |
| 61 | #define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */ |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 62 | |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 63 | /*****************************************************************************/ |
| 64 | /* SOFTWARE API DEFINITION FOR Usart */ |
| 65 | /*****************************************************************************/ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 66 | typedef struct _AT91S_USART |
| 67 | { |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 68 | AT91_REG US_CR; /* Control Register */ |
| 69 | AT91_REG US_MR; /* Mode Register */ |
| 70 | AT91_REG US_IER; /* Interrupt Enable Register */ |
| 71 | AT91_REG US_IDR; /* Interrupt Disable Register */ |
| 72 | AT91_REG US_IMR; /* Interrupt Mask Register */ |
| 73 | AT91_REG US_CSR; /* Channel Status Register */ |
| 74 | AT91_REG US_RHR; /* Receiver Holding Register */ |
| 75 | AT91_REG US_THR; /* Transmitter Holding Register */ |
| 76 | AT91_REG US_BRGR; /* Baud Rate Generator Register */ |
| 77 | AT91_REG US_RTOR; /* Receiver Time-out Register */ |
| 78 | AT91_REG US_TTGR; /* Transmitter Time-guard Register */ |
| 79 | AT91_REG Reserved0[5]; /* */ |
| 80 | AT91_REG US_FIDI; /* FI_DI_Ratio Register */ |
| 81 | AT91_REG US_NER; /* Nb Errors Register */ |
| 82 | AT91_REG US_XXR; /* XON_XOFF Register */ |
| 83 | AT91_REG US_IF; /* IRDA_FILTER Register */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 84 | AT91_REG Reserved1[44]; /* */ |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 85 | AT91_REG US_RPR; /* Receive Pointer Register */ |
| 86 | AT91_REG US_RCR; /* Receive Counter Register */ |
| 87 | AT91_REG US_TPR; /* Transmit Pointer Register */ |
| 88 | AT91_REG US_TCR; /* Transmit Counter Register */ |
| 89 | AT91_REG US_RNPR; /* Receive Next Pointer Register */ |
| 90 | AT91_REG US_RNCR; /* Receive Next Counter Register */ |
| 91 | AT91_REG US_TNPR; /* Transmit Next Pointer Register */ |
| 92 | AT91_REG US_TNCR; /* Transmit Next Counter Register */ |
| 93 | AT91_REG US_PTCR; /* PDC Transfer Control Register */ |
| 94 | AT91_REG US_PTSR; /* PDC Transfer Status Register */ |
Wolfgang Denk | bc650fa | 2005-10-05 01:51:29 +0200 | [diff] [blame] | 95 | } AT91S_USART, *AT91PS_USART; |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 96 | |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 97 | /*****************************************************************************/ |
| 98 | /* SOFTWARE API DEFINITION FOR Clock Generator Controler */ |
| 99 | /*****************************************************************************/ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 100 | typedef struct _AT91S_CKGR |
| 101 | { |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 102 | AT91_REG CKGR_MOR; /* Main Oscillator Register */ |
| 103 | AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ |
| 104 | AT91_REG CKGR_PLLAR; /* PLL A Register */ |
| 105 | AT91_REG CKGR_PLLBR; /* PLL B Register */ |
Wolfgang Denk | bc650fa | 2005-10-05 01:51:29 +0200 | [diff] [blame] | 106 | } AT91S_CKGR, *AT91PS_CKGR; |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 107 | |
| 108 | /* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 109 | #define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) /* (CKGR) Main Oscillator Enable */ |
| 110 | #define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) /* (CKGR) Oscillator Test */ |
| 111 | #define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) /* (CKGR) Main Oscillator Start-up Time */ |
| 112 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 113 | /* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 114 | #define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) /* (CKGR) Main Clock Frequency */ |
| 115 | #define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) /* (CKGR) Main Clock Ready */ |
| 116 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 117 | /* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 118 | #define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ |
| 119 | #define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ |
| 120 | #define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ |
| 121 | #define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL A Counter */ |
| 122 | #define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) /* (CKGR) PLL A Output Frequency Range */ |
| 123 | #define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLA datasheet */ |
| 124 | #define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLA datasheet */ |
| 125 | #define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLA datasheet */ |
| 126 | #define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLA datasheet */ |
| 127 | #define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) /* (CKGR) PLL A Multiplier */ |
| 128 | #define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) /* (CKGR) PLL A Source */ |
| 129 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 130 | /* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 131 | #define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ |
| 132 | #define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ |
| 133 | #define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ |
| 134 | #define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL B Counter */ |
| 135 | #define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) /* (CKGR) PLL B Output Frequency Range */ |
| 136 | #define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLB datasheet */ |
| 137 | #define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLB datasheet */ |
| 138 | #define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLB datasheet */ |
| 139 | #define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLB datasheet */ |
| 140 | #define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) /* (CKGR) PLL B Multiplier */ |
| 141 | #define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */ |
| 142 | #define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */ |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 143 | |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 144 | /*****************************************************************************/ |
| 145 | /* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */ |
| 146 | /*****************************************************************************/ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 147 | typedef struct _AT91S_PIO |
| 148 | { |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 149 | AT91_REG PIO_PER; /* PIO Enable Register */ |
| 150 | AT91_REG PIO_PDR; /* PIO Disable Register */ |
| 151 | AT91_REG PIO_PSR; /* PIO Status Register */ |
| 152 | AT91_REG Reserved0[1]; /* */ |
| 153 | AT91_REG PIO_OER; /* Output Enable Register */ |
| 154 | AT91_REG PIO_ODR; /* Output Disable Registerr */ |
| 155 | AT91_REG PIO_OSR; /* Output Status Register */ |
| 156 | AT91_REG Reserved1[1]; /* */ |
| 157 | AT91_REG PIO_IFER; /* Input Filter Enable Register */ |
| 158 | AT91_REG PIO_IFDR; /* Input Filter Disable Register */ |
| 159 | AT91_REG PIO_IFSR; /* Input Filter Status Register */ |
| 160 | AT91_REG Reserved2[1]; /* */ |
| 161 | AT91_REG PIO_SODR; /* Set Output Data Register */ |
| 162 | AT91_REG PIO_CODR; /* Clear Output Data Register */ |
| 163 | AT91_REG PIO_ODSR; /* Output Data Status Register */ |
| 164 | AT91_REG PIO_PDSR; /* Pin Data Status Register */ |
| 165 | AT91_REG PIO_IER; /* Interrupt Enable Register */ |
| 166 | AT91_REG PIO_IDR; /* Interrupt Disable Register */ |
| 167 | AT91_REG PIO_IMR; /* Interrupt Mask Register */ |
| 168 | AT91_REG PIO_ISR; /* Interrupt Status Register */ |
| 169 | AT91_REG PIO_MDER; /* Multi-driver Enable Register */ |
| 170 | AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ |
| 171 | AT91_REG PIO_MDSR; /* Multi-driver Status Register */ |
| 172 | AT91_REG Reserved3[1]; /* */ |
| 173 | AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ |
| 174 | AT91_REG PIO_PPUER; /* Pull-up Enable Register */ |
| 175 | AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */ |
| 176 | AT91_REG Reserved4[1]; /* */ |
| 177 | AT91_REG PIO_ASR; /* Select A Register */ |
| 178 | AT91_REG PIO_BSR; /* Select B Register */ |
| 179 | AT91_REG PIO_ABSR; /* AB Select Status Register */ |
| 180 | AT91_REG Reserved5[9]; /* */ |
| 181 | AT91_REG PIO_OWER; /* Output Write Enable Register */ |
| 182 | AT91_REG PIO_OWDR; /* Output Write Disable Register */ |
| 183 | AT91_REG PIO_OWSR; /* Output Write Status Register */ |
Wolfgang Denk | bc650fa | 2005-10-05 01:51:29 +0200 | [diff] [blame] | 184 | } AT91S_PIO, *AT91PS_PIO; |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 185 | |
| 186 | |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 187 | /*****************************************************************************/ |
| 188 | /* SOFTWARE API DEFINITION FOR Debug Unit */ |
| 189 | /*****************************************************************************/ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 190 | typedef struct _AT91S_DBGU |
| 191 | { |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 192 | AT91_REG DBGU_CR; /* Control Register */ |
| 193 | AT91_REG DBGU_MR; /* Mode Register */ |
| 194 | AT91_REG DBGU_IER; /* Interrupt Enable Register */ |
| 195 | AT91_REG DBGU_IDR; /* Interrupt Disable Register */ |
| 196 | AT91_REG DBGU_IMR; /* Interrupt Mask Register */ |
| 197 | AT91_REG DBGU_CSR; /* Channel Status Register */ |
| 198 | AT91_REG DBGU_RHR; /* Receiver Holding Register */ |
| 199 | AT91_REG DBGU_THR; /* Transmitter Holding Register */ |
| 200 | AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ |
| 201 | AT91_REG Reserved0[7]; /* */ |
| 202 | AT91_REG DBGU_C1R; /* Chip ID1 Register */ |
| 203 | AT91_REG DBGU_C2R; /* Chip ID2 Register */ |
| 204 | AT91_REG DBGU_FNTR; /* Force NTRST Register */ |
| 205 | AT91_REG Reserved1[45]; /* */ |
| 206 | AT91_REG DBGU_RPR; /* Receive Pointer Register */ |
| 207 | AT91_REG DBGU_RCR; /* Receive Counter Register */ |
| 208 | AT91_REG DBGU_TPR; /* Transmit Pointer Register */ |
| 209 | AT91_REG DBGU_TCR; /* Transmit Counter Register */ |
| 210 | AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ |
| 211 | AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ |
| 212 | AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ |
| 213 | AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ |
| 214 | AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ |
| 215 | AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ |
Wolfgang Denk | bc650fa | 2005-10-05 01:51:29 +0200 | [diff] [blame] | 216 | } AT91S_DBGU, *AT91PS_DBGU; |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 217 | |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 218 | /* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 219 | #define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */ |
| 220 | #define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */ |
| 221 | #define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */ |
| 222 | #define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */ |
| 223 | #define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */ |
| 224 | #define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */ |
| 225 | #define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */ |
| 226 | #define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */ |
| 227 | #define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */ |
| 228 | #define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */ |
| 229 | #define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */ |
| 230 | #define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */ |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 231 | |
| 232 | /* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 233 | #define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */ |
| 234 | #define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */ |
| 235 | #define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */ |
| 236 | #define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */ |
| 237 | #define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */ |
| 238 | #define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */ |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 239 | |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 240 | #define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */ |
| 241 | #define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */ |
| 242 | #define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */ |
| 243 | #define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */ |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 244 | |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 245 | /*****************************************************************************/ |
| 246 | /* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */ |
| 247 | /*****************************************************************************/ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 248 | typedef struct _AT91S_SMC2 |
| 249 | { |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 250 | AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ |
Wolfgang Denk | bc650fa | 2005-10-05 01:51:29 +0200 | [diff] [blame] | 251 | } AT91S_SMC2, *AT91PS_SMC2; |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 252 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 253 | /* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 254 | #define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */ |
| 255 | #define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ |
| 256 | #define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */ |
| 257 | #define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */ |
| 258 | #define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */ |
| 259 | #define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */ |
| 260 | #define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ |
| 261 | #define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */ |
| 262 | #define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */ |
| 263 | #define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ |
| 264 | #define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */ |
| 265 | #define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */ |
| 266 | #define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */ |
| 267 | #define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */ |
| 268 | #define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */ |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 269 | |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 270 | /*****************************************************************************/ |
| 271 | /* SOFTWARE API DEFINITION FOR Power Management Controler */ |
| 272 | /*****************************************************************************/ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 273 | typedef struct _AT91S_PMC |
| 274 | { |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 275 | AT91_REG PMC_SCER; /* System Clock Enable Register */ |
| 276 | AT91_REG PMC_SCDR; /* System Clock Disable Register */ |
| 277 | AT91_REG PMC_SCSR; /* System Clock Status Register */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 278 | AT91_REG Reserved0[1]; /* */ |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 279 | AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ |
| 280 | AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ |
| 281 | AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 282 | AT91_REG Reserved1[5]; /* */ |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 283 | AT91_REG PMC_MCKR; /* Master Clock Register */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 284 | AT91_REG Reserved2[3]; /* */ |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 285 | AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */ |
| 286 | AT91_REG PMC_IER; /* Interrupt Enable Register */ |
| 287 | AT91_REG PMC_IDR; /* Interrupt Disable Register */ |
| 288 | AT91_REG PMC_SR; /* Status Register */ |
| 289 | AT91_REG PMC_IMR; /* Interrupt Mask Register */ |
Wolfgang Denk | bc650fa | 2005-10-05 01:51:29 +0200 | [diff] [blame] | 290 | } AT91S_PMC, *AT91PS_PMC; |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 291 | |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 292 | /*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 293 | #define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) /* (PMC) Processor Clock */ |
| 294 | #define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) /* (PMC) USB Device Port Clock */ |
| 295 | #define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */ |
| 296 | #define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) /* (PMC) USB Host Port Clock */ |
| 297 | #define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) /* (PMC) Programmable Clock Output */ |
| 298 | #define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) /* (PMC) Programmable Clock Output */ |
| 299 | #define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */ |
| 300 | #define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */ |
| 301 | #define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */ |
| 302 | #define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */ |
| 303 | #define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */ |
| 304 | #define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */ |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 305 | /*-------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ------*/ |
| 306 | /*-------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------*/ |
| 307 | /*-------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 308 | #define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) /* (PMC) Programmable Clock Selection */ |
| 309 | #define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) /* (PMC) Slow Clock is selected */ |
| 310 | #define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) /* (PMC) Main Clock is selected */ |
| 311 | #define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) /* (PMC) Clock from PLL A is selected */ |
| 312 | #define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) /* (PMC) Clock from PLL B is selected */ |
| 313 | #define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) /* (PMC) Programmable Clock Prescaler */ |
| 314 | #define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) /* (PMC) Selected clock */ |
| 315 | #define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) /* (PMC) Selected clock divided by 2 */ |
| 316 | #define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) /* (PMC) Selected clock divided by 4 */ |
| 317 | #define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) /* (PMC) Selected clock divided by 8 */ |
| 318 | #define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) /* (PMC) Selected clock divided by 16 */ |
| 319 | #define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) /* (PMC) Selected clock divided by 32 */ |
| 320 | #define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) /* (PMC) Selected clock divided by 64 */ |
| 321 | #define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) /* (PMC) Master Clock Division */ |
| 322 | #define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) /* (PMC) The master clock and the processor clock are the same */ |
| 323 | #define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) /* (PMC) The processor clock is twice as fast as the master clock */ |
| 324 | #define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) /* (PMC) The processor clock is three times faster than the master clock */ |
| 325 | #define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) /* (PMC) The processor clock is four times faster than the master clock */ |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 326 | /*------ PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/ |
| 327 | /*------ PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------*/ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 328 | #define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask */ |
| 329 | #define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) /* (PMC) PLL A Status/Enable/Disable/Mask */ |
| 330 | #define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) /* (PMC) PLL B Status/Enable/Disable/Mask */ |
| 331 | #define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ |
| 332 | #define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ |
| 333 | #define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ |
| 334 | #define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ |
| 335 | #define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ |
| 336 | #define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */ |
| 337 | #define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */ |
| 338 | #define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */ |
| 339 | #define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */ |
wdenk | 20dd2fa | 2004-11-21 00:06:33 +0000 | [diff] [blame] | 340 | /*---- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/ |
| 341 | /*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/ |
| 342 | /*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/ |
| 343 | |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 344 | /*****************************************************************************/ |
| 345 | /* SOFTWARE API DEFINITION FOR Ethernet MAC */ |
| 346 | /*****************************************************************************/ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 347 | typedef struct _AT91S_EMAC |
| 348 | { |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 349 | AT91_REG EMAC_CTL; /* Network Control Register */ |
| 350 | AT91_REG EMAC_CFG; /* Network Configuration Register */ |
| 351 | AT91_REG EMAC_SR; /* Network Status Register */ |
| 352 | AT91_REG EMAC_TAR; /* Transmit Address Register */ |
| 353 | AT91_REG EMAC_TCR; /* Transmit Control Register */ |
| 354 | AT91_REG EMAC_TSR; /* Transmit Status Register */ |
| 355 | AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ |
| 356 | AT91_REG Reserved0[1]; /* */ |
| 357 | AT91_REG EMAC_RSR; /* Receive Status Register */ |
| 358 | AT91_REG EMAC_ISR; /* Interrupt Status Register */ |
| 359 | AT91_REG EMAC_IER; /* Interrupt Enable Register */ |
| 360 | AT91_REG EMAC_IDR; /* Interrupt Disable Register */ |
| 361 | AT91_REG EMAC_IMR; /* Interrupt Mask Register */ |
| 362 | AT91_REG EMAC_MAN; /* PHY Maintenance Register */ |
| 363 | AT91_REG Reserved1[2]; /* */ |
| 364 | AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */ |
| 365 | AT91_REG EMAC_SCOL; /* Single Collision Frame Register */ |
| 366 | AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */ |
| 367 | AT91_REG EMAC_OK; /* Frames Received OK Register */ |
| 368 | AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */ |
| 369 | AT91_REG EMAC_ALE; /* Alignment Error Register */ |
| 370 | AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */ |
| 371 | AT91_REG EMAC_LCOL; /* Late Collision Register */ |
| 372 | AT91_REG EMAC_ECOL; /* Excessive Collision Register */ |
| 373 | AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ |
| 374 | AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */ |
| 375 | AT91_REG EMAC_CDE; /* Code Error Register */ |
| 376 | AT91_REG EMAC_ELR; /* Excessive Length Error Register */ |
| 377 | AT91_REG EMAC_RJB; /* Receive Jabber Register */ |
| 378 | AT91_REG EMAC_USF; /* Undersize Frame Register */ |
| 379 | AT91_REG EMAC_SQEE; /* SQE Test Error Register */ |
| 380 | AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */ |
| 381 | AT91_REG Reserved2[3]; /* */ |
| 382 | AT91_REG EMAC_HSH; /* Hash Address High[63:32] */ |
| 383 | AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */ |
| 384 | AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */ |
| 385 | AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */ |
| 386 | AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */ |
| 387 | AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */ |
| 388 | AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */ |
| 389 | AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */ |
| 390 | AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */ |
| 391 | AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */ |
Wolfgang Denk | bc650fa | 2005-10-05 01:51:29 +0200 | [diff] [blame] | 392 | } AT91S_EMAC, *AT91PS_EMAC; |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 393 | |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 394 | /* -------- EMAC_CTL : (EMAC Offset: 0x0) -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 395 | #define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ |
| 396 | #define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) /* (EMAC) Loopback local. */ |
| 397 | #define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */ |
| 398 | #define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */ |
| 399 | #define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */ |
| 400 | #define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */ |
| 401 | #define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) /* (EMAC) Increment statistics registers. */ |
| 402 | #define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) /* (EMAC) Write enable for statistics registers. */ |
| 403 | #define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) /* (EMAC) Back pressure. */ |
| 404 | |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 405 | /* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 406 | #define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */ |
| 407 | #define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */ |
| 408 | #define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) /* (EMAC) Bit rate. */ |
| 409 | #define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */ |
| 410 | #define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */ |
| 411 | #define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) /* (EMAC) Multicast hash enable */ |
| 412 | #define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) /* (EMAC) Unicast hash enable. */ |
| 413 | #define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) /* (EMAC) Receive 1522 bytes. */ |
| 414 | #define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) /* (EMAC) External address match enable. */ |
| 415 | #define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */ |
| 416 | #define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */ |
| 417 | #define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */ |
| 418 | #define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */ |
| 419 | #define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */ |
| 420 | #define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) /* (EMAC) */ |
| 421 | #define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */ |
| 422 | |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 423 | /* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 424 | #define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */ |
| 425 | #define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */ |
| 426 | |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 427 | /* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register ------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 428 | #define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */ |
| 429 | #define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */ |
| 430 | |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 431 | /* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register ------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 432 | #define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */ |
| 433 | #define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */ |
| 434 | #define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */ |
| 435 | #define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) /* (EMAC) */ |
| 436 | #define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */ |
| 437 | #define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */ |
| 438 | #define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) /* (EMAC) */ |
| 439 | |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 440 | /* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 441 | #define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */ |
| 442 | #define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */ |
| 443 | #define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */ |
| 444 | |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 445 | /* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register ------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 446 | #define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */ |
| 447 | #define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */ |
| 448 | #define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */ |
| 449 | #define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) /* (EMAC) */ |
| 450 | #define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) /* (EMAC) */ |
| 451 | #define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) /* (EMAC) */ |
| 452 | #define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) /* (EMAC) */ |
| 453 | #define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) /* (EMAC) */ |
| 454 | #define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) /* (EMAC) */ |
| 455 | #define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) /* (EMAC) */ |
| 456 | #define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */ |
| 457 | #define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */ |
| 458 | |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 459 | /* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register ------- */ |
| 460 | /* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register ------ */ |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 461 | /* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ |
| 462 | /* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 463 | #define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */ |
| 464 | #define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) /* (EMAC) */ |
| 465 | #define AT91C_EMAC_CODE_802_3 ((unsigned int) 0x2 << 16) /* (EMAC) Write Operation */ |
| 466 | #define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) /* (EMAC) */ |
| 467 | #define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) /* (EMAC) */ |
| 468 | #define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) /* (EMAC) */ |
| 469 | #define AT91C_EMAC_RW_R ((unsigned int) 0x2 << 28) /* (EMAC) Read Operation */ |
| 470 | #define AT91C_EMAC_RW_W ((unsigned int) 0x1 << 28) /* (EMAC) Write Operation */ |
| 471 | #define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */ |
| 472 | #define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */ |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 473 | |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 474 | /*****************************************************************************/ |
| 475 | /* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ |
| 476 | /*****************************************************************************/ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 477 | typedef struct _AT91S_SPI |
| 478 | { |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 479 | AT91_REG SPI_CR; /* Control Register */ |
| 480 | AT91_REG SPI_MR; /* Mode Register */ |
| 481 | AT91_REG SPI_RDR; /* Receive Data Register */ |
| 482 | AT91_REG SPI_TDR; /* Transmit Data Register */ |
| 483 | AT91_REG SPI_SR; /* Status Register */ |
| 484 | AT91_REG SPI_IER; /* Interrupt Enable Register */ |
| 485 | AT91_REG SPI_IDR; /* Interrupt Disable Register */ |
| 486 | AT91_REG SPI_IMR; /* Interrupt Mask Register */ |
| 487 | AT91_REG Reserved0[4]; /* */ |
| 488 | AT91_REG SPI_CSR[4]; /* Chip Select Register */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 489 | AT91_REG Reserved1[48]; /* */ |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 490 | AT91_REG SPI_RPR; /* Receive Pointer Register */ |
| 491 | AT91_REG SPI_RCR; /* Receive Counter Register */ |
| 492 | AT91_REG SPI_TPR; /* Transmit Pointer Register */ |
| 493 | AT91_REG SPI_TCR; /* Transmit Counter Register */ |
| 494 | AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ |
| 495 | AT91_REG SPI_RNCR; /* Receive Next Counter Register */ |
| 496 | AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ |
| 497 | AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ |
| 498 | AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ |
| 499 | AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ |
Wolfgang Denk | bc650fa | 2005-10-05 01:51:29 +0200 | [diff] [blame] | 500 | } AT91S_SPI, *AT91PS_SPI; |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 501 | |
| 502 | /* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 503 | #define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) /* (SPI) SPI Enable */ |
| 504 | #define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) /* (SPI) SPI Disable */ |
| 505 | #define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) /* (SPI) SPI Software reset */ |
| 506 | |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 507 | /* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 508 | #define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) /* (SPI) Master/Slave Mode */ |
| 509 | #define AT91C_SPI_PS ((unsigned int) 0x1 << 1) /* (SPI) Peripheral Select */ |
| 510 | #define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) /* (SPI) Fixed Peripheral Select */ |
| 511 | #define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) /* (SPI) Variable Peripheral Select */ |
| 512 | #define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) /* (SPI) Chip Select Decode */ |
| 513 | #define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) /* (SPI) Clock Selection */ |
| 514 | #define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) /* (SPI) Mode Fault Detection */ |
| 515 | #define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) /* (SPI) Clock Selection */ |
| 516 | #define AT91C_SPI_PCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */ |
| 517 | #define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */ |
| 518 | |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 519 | /* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 520 | #define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) /* (SPI) Receive Data */ |
| 521 | #define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */ |
| 522 | |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 523 | /* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 524 | #define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) /* (SPI) Transmit Data */ |
| 525 | #define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */ |
| 526 | |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 527 | /* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 528 | #define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) /* (SPI) Receive Data Register Full */ |
| 529 | #define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) /* (SPI) Transmit Data Register Empty */ |
| 530 | #define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) /* (SPI) Mode Fault Error */ |
| 531 | #define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) /* (SPI) Overrun Error Status */ |
| 532 | #define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) /* (SPI) End of Receiver Transfer */ |
| 533 | #define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) /* (SPI) End of Receiver Transfer */ |
| 534 | #define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) /* (SPI) RXBUFF Interrupt */ |
| 535 | #define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) /* (SPI) TXBUFE Interrupt */ |
| 536 | #define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */ |
| 537 | |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 538 | /* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 539 | /* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register ------- */ |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 540 | /* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ |
| 541 | /* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 542 | #define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */ |
| 543 | #define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) /* (SPI) Clock Phase */ |
| 544 | #define AT91C_SPI_BITS ((unsigned int) 0xF << 4) /* (SPI) Bits Per Transfer */ |
| 545 | #define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) /* (SPI) 8 Bits Per transfer */ |
| 546 | #define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) /* (SPI) 9 Bits Per transfer */ |
| 547 | #define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) /* (SPI) 10 Bits Per transfer */ |
| 548 | #define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) /* (SPI) 11 Bits Per transfer */ |
| 549 | #define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) /* (SPI) 12 Bits Per transfer */ |
| 550 | #define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) /* (SPI) 13 Bits Per transfer */ |
| 551 | #define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) /* (SPI) 14 Bits Per transfer */ |
| 552 | #define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) /* (SPI) 15 Bits Per transfer */ |
| 553 | #define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) /* (SPI) 16 Bits Per transfer */ |
| 554 | #define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) /* (SPI) Serial Clock Baud Rate */ |
| 555 | #define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */ |
| 556 | #define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */ |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 557 | |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 558 | /*****************************************************************************/ |
| 559 | /* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ |
| 560 | /*****************************************************************************/ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 561 | typedef struct _AT91S_PDC |
| 562 | { |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 563 | AT91_REG PDC_RPR; /* Receive Pointer Register */ |
| 564 | AT91_REG PDC_RCR; /* Receive Counter Register */ |
| 565 | AT91_REG PDC_TPR; /* Transmit Pointer Register */ |
| 566 | AT91_REG PDC_TCR; /* Transmit Counter Register */ |
| 567 | AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ |
| 568 | AT91_REG PDC_RNCR; /* Receive Next Counter Register */ |
| 569 | AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ |
| 570 | AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ |
| 571 | AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ |
| 572 | AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ |
Wolfgang Denk | bc650fa | 2005-10-05 01:51:29 +0200 | [diff] [blame] | 573 | } AT91S_PDC, *AT91PS_PDC; |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 574 | |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 575 | /* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 576 | #define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) /* (PDC) Receiver Transfer Enable */ |
| 577 | #define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) /* (PDC) Receiver Transfer Disable */ |
| 578 | #define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) /* (PDC) Transmitter Transfer Enable */ |
| 579 | #define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) /* (PDC) Transmitter Transfer Disable */ |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 580 | /* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 581 | |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 582 | /* ========== Register definition ==================================== */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 583 | #define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) /* (SPI) Chip Select Register */ |
| 584 | #define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */ |
Wolfgang Denk | 8a6820a | 2005-09-26 01:26:56 +0200 | [diff] [blame] | 585 | #define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) /* (PMC) Peripheral Clock Enable Register */ |
| 586 | #define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) /* (PMC) Peripheral Clock Enable Register */ |
| 587 | #define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) /* (PMC) Peripheral Clock Enable Register */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 588 | #define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) /* (PIOA) PIO Enable Register */ |
| 589 | #define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */ |
| 590 | #define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) /* (PIOA) PIO Status Register */ |
| 591 | #define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) /* (PIOA) PIO Output Enable Register */ |
| 592 | #define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) /* (PIOA) PIO Output Disable Register */ |
| 593 | #define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) /* (PIOA) PIO Output Status Register */ |
| 594 | #define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) /* (PIOA) PIO Glitch Input Filter Enable Register */ |
| 595 | #define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) /* (PIOA) PIO Glitch Input Filter Disable Register */ |
| 596 | #define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) /* (PIOA) PIO Glitch Input Filter Status Register */ |
| 597 | #define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) /* (PIOA) PIO Set Output Data Register */ |
| 598 | #define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) /* (PIOA) PIO Clear Output Data Register */ |
| 599 | #define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) /* (PIOA) PIO Output Data Status Register */ |
| 600 | #define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) /* (PIOA) PIO Pin Data Status Register */ |
| 601 | #define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) /* (PIOA) PIO Interrupt Enable Register */ |
| 602 | #define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) /* (PIOA) PIO Interrupt Disable Register */ |
| 603 | #define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) /* (PIOA) PIO Interrupt Mask Register */ |
| 604 | #define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) /* (PIOA) PIO Interrupt Status Register */ |
| 605 | #define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) /* (PIOA) PIO Multi-drive Enable Register */ |
| 606 | #define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) /* (PIOA) PIO Multi-drive Disable Register */ |
| 607 | #define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) /* (PIOA) PIO Multi-drive Status Register */ |
| 608 | #define AT91C_PIOA_PUDR ((AT91_REG *) 0xFFFFF460) /* (PIOA) PIO Pull-up Disable Register */ |
| 609 | #define AT91C_PIOA_PUER ((AT91_REG *) 0xFFFFF464) /* (PIOA) PIO Pull-up Enable Register */ |
| 610 | #define AT91C_PIOA_PUSR ((AT91_REG *) 0xFFFFF468) /* (PIOA) PIO Pull-up Status Register */ |
| 611 | #define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) /* (PIOA) PIO Peripheral A Select Register */ |
| 612 | #define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) /* (PIOA) PIO Peripheral B Select Register */ |
| 613 | #define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) /* (PIOA) PIO Peripheral AB Select Register */ |
| 614 | #define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) /* (PIOA) PIO Output Write Enable Register */ |
| 615 | #define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) /* (PIOA) PIO Output Write Disable Register */ |
| 616 | #define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) /* (PIOA) PIO Output Write Status Register */ |
| 617 | #define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 618 | |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 619 | #define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */ |
| 620 | #define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */ |
| 621 | #define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) /* Burst Flash Clock */ |
| 622 | #define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) /* DBGU Debug Receive Data */ |
| 623 | #define AT91C_PIO_PA31 ((unsigned int) 1 << 31) /* Pin Controlled by PA31 */ |
wdenk | 70ae5b4 | 2004-10-10 17:05:18 +0000 | [diff] [blame] | 624 | #define AT91C_PA25_TWD ((unsigned int) 1 << 25) |
| 625 | #define AT91C_PA26_TWCK ((unsigned int) 1 << 26) |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 626 | #define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */ |
| 627 | #define AT91C_PIO_PA17 ((unsigned int) 1 << 17) /* Pin Controlled by PA17 */ |
| 628 | #define AT91C_PA17_TXD0 AT91C_PIO_PA17 /* USART0 Transmit Data */ |
| 629 | #define AT91C_PIO_PA18 ((unsigned int) 1 << 18) /* Pin Controlled by PA18 */ |
| 630 | #define AT91C_PA18_RXD0 AT91C_PIO_PA18 /* USART0 Receive Data */ |
| 631 | #define AT91C_PIO_PB20 ((unsigned int) 1 << 20) /* Pin Controlled by PB20 */ |
| 632 | #define AT91C_PB20_RXD1 AT91C_PIO_PB20 /* USART1 Receive Data */ |
| 633 | #define AT91C_PIO_PB21 ((unsigned int) 1 << 21) /* Pin Controlled by PB21 */ |
| 634 | #define AT91C_PB21_TXD1 AT91C_PIO_PB21 /* USART1 Transmit Data */ |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 635 | |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 636 | #define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */ |
| 637 | #define AT91C_ID_PIOA ((unsigned int) 2) /* PIO port A */ |
| 638 | #define AT91C_ID_PIOB ((unsigned int) 3) /* PIO port B */ |
| 639 | #define AT91C_ID_PIOC ((unsigned int) 4) /* PIO port C */ |
| 640 | #define AT91C_ID_USART0 ((unsigned int) 6) /* USART 0 */ |
| 641 | #define AT91C_ID_USART1 ((unsigned int) 7) /* USART 1 */ |
| 642 | #define AT91C_ID_TWI ((unsigned int) 12) /* Two Wire Interface */ |
| 643 | #define AT91C_ID_SPI ((unsigned int) 13) /* Serial Peripheral Interface */ |
| 644 | #define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */ |
Wolfgang Denk | 8a6820a | 2005-09-26 01:26:56 +0200 | [diff] [blame] | 645 | #define AT91C_ID_UHP ((unsigned int) 23) /* OHCI USB Host Port */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 646 | #define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */ |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 647 | |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 648 | #define AT91C_PIO_PC1 ((unsigned int) 1 << 1) /* Pin Controlled by PC1 */ |
| 649 | #define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /* Burst Flash Ready */ |
| 650 | #define AT91C_PIO_PC3 ((unsigned int) 1 << 3) /* Pin Controlled by PC3 */ |
| 651 | #define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /* Burst Flash Address Advance / SmartMedia Write Enable */ |
| 652 | #define AT91C_PIO_PC2 ((unsigned int) 1 << 2) /* Pin Controlled by PC2 */ |
| 653 | #define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) /* Burst Flash Address Valid */ |
| 654 | #define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB1 */ |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 655 | |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 656 | #define AT91C_PIO_PA23 ((unsigned int) 1 << 23) /* Pin Controlled by PA23 */ |
| 657 | #define AT91C_PA23_TXD2 ((unsigned int) AT91C_PIO_PA23) /* USART 2 Transmit Data */ |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 658 | |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 659 | #define AT91C_PIO_PA0 ((unsigned int) 1 << 0) /* Pin Controlled by PA0 */ |
| 660 | #define AT91C_PA0_MISO ((unsigned int) AT91C_PIO_PA0) /* SPI Master In Slave */ |
| 661 | #define AT91C_PIO_PA1 ((unsigned int) 1 << 1) /* Pin Controlled by PA1 */ |
| 662 | #define AT91C_PA1_MOSI ((unsigned int) AT91C_PIO_PA1) /* SPI Master Out Slave */ |
| 663 | #define AT91C_PIO_PA2 ((unsigned int) 1 << 2) /* Pin Controlled by PA2 */ |
| 664 | #define AT91C_PA2_SPCK ((unsigned int) AT91C_PIO_PA2) /* SPI Serial Clock */ |
| 665 | #define AT91C_PIO_PA3 ((unsigned int) 1 << 3) /* Pin Controlled by PA3 */ |
| 666 | #define AT91C_PA3_NPCS0 ((unsigned int) AT91C_PIO_PA3) /* SPI Peripheral Chip Select 0 */ |
| 667 | #define AT91C_PIO_PA4 ((unsigned int) 1 << 4) /* Pin Controlled by PA4 */ |
| 668 | #define AT91C_PA4_NPCS1 ((unsigned int) AT91C_PIO_PA4) /* SPI Peripheral Chip Select 1 */ |
| 669 | #define AT91C_PIO_PA5 ((unsigned int) 1 << 5) /* Pin Controlled by PA5 */ |
| 670 | #define AT91C_PA5_NPCS2 ((unsigned int) AT91C_PIO_PA5) /* SPI Peripheral Chip Select 2 */ |
| 671 | #define AT91C_PIO_PA6 ((unsigned int) 1 << 6) /* Pin Controlled by PA6 */ |
| 672 | #define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) /* SPI Peripheral Chip Select 3 */ |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 673 | |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 674 | #define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */ |
| 675 | #define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */ |
| 676 | #define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */ |
| 677 | #define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */ |
| 678 | #define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */ |
| 679 | #define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */ |
| 680 | #define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */ |
| 681 | #define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */ |
| 682 | #define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */ |
| 683 | #define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */ |
| 684 | #define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */ |
| 685 | #define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ |
| 686 | #define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */ |
| 687 | #define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */ |
| 688 | #define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */ |
| 689 | #define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0 */ |
| 690 | #define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8 */ |
| 691 | #define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */ |
| 692 | #define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */ |
| 693 | #define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */ |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 694 | |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 695 | #define AT91C_PIO_PB0 ((unsigned int) 1 << 0) /* Pin Controlled by PB3 */ |
| 696 | #define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB3 */ |
| 697 | #define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PB3 */ |
Wolfgang Denk | bc650fa | 2005-10-05 01:51:29 +0200 | [diff] [blame] | 698 | #define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */ |
| 699 | #define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */ |
| 700 | #define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */ |
| 701 | #define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 702 | #define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */ |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 703 | #define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 704 | #define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */ |
| 705 | #define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */ |
| 706 | #define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */ |
| 707 | #define AT91C_PIO_PB19 ((unsigned int) 1 << 19) /* Pin Controlled by PB19 */ |
| 708 | #define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) /* USART 1 Data Terminal ready */ |
| 709 | #define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) /* Ethernet MAC Receive Clock */ |
| 710 | #define AT91C_PIO_PB18 ((unsigned int) 1 << 18) /* Pin Controlled by PB18 */ |
| 711 | #define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) /* USART 1 Ring Indicator */ |
| 712 | #define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) /* Ethernet MAC Collision Detected */ |
| 713 | #define AT91C_PIO_PB17 ((unsigned int) 1 << 17) /* Pin Controlled by PB17 */ |
| 714 | #define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) /* SSC Receive Frame Sync 2 */ |
| 715 | #define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) /* Ethernet MAC Receive Data Valid */ |
| 716 | #define AT91C_PIO_PB16 ((unsigned int) 1 << 16) /* Pin Controlled by PB16 */ |
| 717 | #define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) /* SSC Receive Clock 2 */ |
| 718 | #define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) /* Ethernet MAC Receive Data 3 */ |
| 719 | #define AT91C_PIO_PB15 ((unsigned int) 1 << 15) /* Pin Controlled by PB15 */ |
| 720 | #define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) /* SSC Receive Data 2 */ |
| 721 | #define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) /* Ethernet MAC Receive Data 2 */ |
| 722 | #define AT91C_PIO_PB14 ((unsigned int) 1 << 14) /* Pin Controlled by PB14 */ |
| 723 | #define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) /* SSC Transmit Data 2 */ |
| 724 | #define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */ |
| 725 | #define AT91C_PIO_PB13 ((unsigned int) 1 << 13) /* Pin Controlled by PB13 */ |
| 726 | #define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) /* SSC Transmit Clock 2 */ |
| 727 | #define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) /* Ethernet MAC Transmit Data 3 */ |
| 728 | #define AT91C_PIO_PB12 ((unsigned int) 1 << 12) /* Pin Controlled by PB12 */ |
| 729 | #define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */ |
| 730 | #define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */ |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 731 | |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 732 | #define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */ |
| 733 | #define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 734 | |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 735 | #define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */ |
| 736 | #define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ |
| 737 | #define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ |
| 738 | #define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ |
| 739 | #define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */ |
| 740 | #define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */ |
| 741 | #define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */ |
| 742 | #define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */ |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 743 | |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 744 | #define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) /* (AIC) Base Address */ |
| 745 | #define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */ |
| 746 | #define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */ |
| 747 | #define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */ |
| 748 | #define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */ |
| 749 | #define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) /* (PIOC) Base Address */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 750 | #define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */ |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 751 | #if 0 |
| 752 | #define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) /* (PMC) Base Address */ |
| 753 | #define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) /* (PMC) Base Address */ |
| 754 | #define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) /* (PMC) Base Address */ |
| 755 | #endif |
| 756 | |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 757 | #define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */ |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame^] | 758 | #define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA4000) /* (TC0) Base Address */ |
| 759 | #if 0 |
| 760 | #define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) /* (TC0) Base Address */ |
| 761 | #define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) /* (TC0) Base Address */ |
| 762 | #define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) /* (TC0) Base Address */ |
| 763 | #endif |
| 764 | #define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */ |
| 765 | #define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */ |
| 766 | #define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */ |
| 767 | #define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) /* (US1) Base Address */ |
| 768 | #define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) /* (US1) Base Address */ |
| 769 | #define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */ |
| 770 | |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 771 | #define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 772 | #define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */ |
| 773 | #define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */ |
Wolfgang Denk | 712fb8e | 2005-09-25 17:14:20 +0200 | [diff] [blame] | 774 | #define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */ |
| 775 | #define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */ |
| 776 | #define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */ |
| 777 | #define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */ |
| 778 | #define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */ |
| 779 | #define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */ |
| 780 | #define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ |
| 781 | #define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ |
wdenk | 381669a | 2003-06-16 23:50:08 +0000 | [diff] [blame] | 782 | |
wdenk | 8dba050 | 2003-03-31 16:34:49 +0000 | [diff] [blame] | 783 | #endif |