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git01.mediatek.com / filogic / uboot / de2ca03d8687ca71c5b0d7b132f88c0831d09688 / . / arch / arm / dts / imx8mq-kontron-pitx-imx8m.dts
blob: e8fbf0ec6d68f576f96273a0966c151a8b39ede0 [file] [log] [blame]
Heiko Thiery05a3d952022-01-31 17:30:45 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree File for the Kontron pitx-imx8m board.
4 *
5 * Copyright (C) 2021 Heiko Thiery <heiko.thiery@gmail.com>
6 */
7
8/dts-v1/;
9
10#include "imx8mq.dtsi"
11#include <dt-bindings/net/ti-dp83867.h>
12
13/ {
14 model = "Kontron pITX-imx8m";
15 compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
16
17 aliases {
18 i2c0 = &i2c1;
19 i2c1 = &i2c2;
20 i2c2 = &i2c3;
21 mmc0 = &usdhc1;
22 mmc1 = &usdhc2;
23 serial0 = &uart1;
24 serial1 = &uart2;
25 serial2 = &uart3;
26 spi0 = &qspi0;
27 spi1 = &ecspi2;
28 };
29
30 chosen {
31 stdout-path = "serial2:115200n8";
32 };
33
34 pcie0_refclk: pcie0-clock {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <100000000>;
38 };
39
40 pcie1_refclk: pcie1-clock {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <100000000>;
44 };
45
46 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
47 compatible = "regulator-fixed";
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_reg_usdhc2>;
50 regulator-name = "V_3V3_SD";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
54 enable-active-high;
55 };
56};
57
58&ecspi2 {
59 #address-cells = <1>;
60 #size-cells = <0>;
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
63 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
64 status = "okay";
65
66 tpm@0 {
67 compatible = "infineon,slb9670";
68 reg = <0>;
69 spi-max-frequency = <43000000>;
70 };
71};
72
73&fec1 {
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_fec1>;
76 phy-mode = "rgmii-id";
77 phy-handle = <&ethphy0>;
78 fsl,magic-packet;
79 status = "okay";
80
81 mdio {
82 #address-cells = <1>;
83 #size-cells = <0>;
84
85 ethphy0: ethernet-phy@0 {
86 compatible = "ethernet-phy-ieee802.3-c22";
87 reg = <0>;
88 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
89 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
90 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
91 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
92 reset-assert-us = <10>;
93 reset-deassert-us = <280>;
94 };
95 };
96};
97
98&i2c1 {
99 clock-frequency = <400000>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_i2c1>;
102 status = "okay";
103
104 pmic@8 {
105 compatible = "fsl,pfuze100";
106 fsl,pfuze-support-disable-sw;
107 reg = <0x8>;
108
109 regulators {
110 sw1a_reg: sw1ab {
111 regulator-name = "V_0V9_GPU";
112 regulator-min-microvolt = <825000>;
113 regulator-max-microvolt = <1100000>;
114 };
115
116 sw1c_reg: sw1c {
117 regulator-name = "V_0V9_VPU";
118 regulator-min-microvolt = <825000>;
119 regulator-max-microvolt = <1100000>;
120 };
121
122 sw2_reg: sw2 {
123 regulator-name = "V_1V1_NVCC_DRAM";
124 regulator-min-microvolt = <1100000>;
125 regulator-max-microvolt = <1100000>;
126 regulator-always-on;
127 };
128
129 sw3a_reg: sw3ab {
130 regulator-name = "V_1V0_DRAM";
131 regulator-min-microvolt = <825000>;
132 regulator-max-microvolt = <1100000>;
133 regulator-always-on;
134 };
135
136 sw4_reg: sw4 {
137 regulator-name = "V_1V8_S0";
138 regulator-min-microvolt = <1800000>;
139 regulator-max-microvolt = <1800000>;
140 regulator-always-on;
141 };
142
143 swbst_reg: swbst {
144 regulator-name = "NC";
145 regulator-min-microvolt = <5000000>;
146 regulator-max-microvolt = <5150000>;
147 };
148
149 snvs_reg: vsnvs {
150 regulator-name = "V_0V9_SNVS";
151 regulator-min-microvolt = <1000000>;
152 regulator-max-microvolt = <3000000>;
153 regulator-always-on;
154 };
155
156 vref_reg: vrefddr {
157 regulator-name = "V_0V55_VREF_DDR";
158 regulator-always-on;
159 };
160
161 vgen1_reg: vgen1 {
162 regulator-name = "V_1V5_CSI";
163 regulator-min-microvolt = <800000>;
164 regulator-max-microvolt = <1550000>;
165 };
166
167 vgen2_reg: vgen2 {
168 regulator-name = "V_0V9_PHY";
169 regulator-min-microvolt = <850000>;
170 regulator-max-microvolt = <975000>;
171 regulator-always-on;
172 };
173
174 vgen3_reg: vgen3 {
175 regulator-name = "V_1V8_PHY";
176 regulator-min-microvolt = <1675000>;
177 regulator-max-microvolt = <1975000>;
178 regulator-always-on;
179 };
180
181 vgen4_reg: vgen4 {
182 regulator-name = "V_1V8_VDDA";
183 regulator-min-microvolt = <1625000>;
184 regulator-max-microvolt = <1875000>;
185 regulator-always-on;
186 };
187
188 vgen5_reg: vgen5 {
189 regulator-name = "V_3V3_PHY";
190 regulator-min-microvolt = <3075000>;
191 regulator-max-microvolt = <3625000>;
192 regulator-always-on;
193 };
194
195 vgen6_reg: vgen6 {
196 regulator-name = "V_2V8_CAM";
197 regulator-min-microvolt = <1800000>;
198 regulator-max-microvolt = <3300000>;
199 regulator-always-on;
200 };
201 };
202 };
203
204 fan-controller@1b {
205 compatible = "maxim,max6650";
206 reg = <0x1b>;
207 maxim,fan-microvolt = <5000000>;
208 };
209
210 rtc@32 {
211 compatible = "microcrystal,rv8803";
212 reg = <0x32>;
213 };
214
215 sensor@4b {
216 compatible = "national,lm75b";
217 reg = <0x4b>;
218 };
219
220 eeprom@51 {
221 compatible = "atmel,24c32";
222 reg = <0x51>;
223 pagesize = <32>;
224 };
225};
226
227&i2c2 {
228 clock-frequency = <100000>;
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_i2c2>;
231 status = "okay";
232};
233
234&i2c3 {
235 clock-frequency = <100000>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_i2c3>;
238 status = "okay";
239};
240
241/* M.2 B-key slot */
242&pcie0 {
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_pcie0>;
245 reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
246 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
247 <&clk IMX8MQ_CLK_PCIE1_AUX>,
248 <&clk IMX8MQ_CLK_PCIE1_PHY>,
249 <&pcie0_refclk>;
250 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
251 status = "okay";
252};
253
254/* Intel Ethernet Controller I210/I211 */
255&pcie1 {
256 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
257 <&clk IMX8MQ_CLK_PCIE2_AUX>,
258 <&clk IMX8MQ_CLK_PCIE2_PHY>,
259 <&pcie1_refclk>;
260 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
261 fsl,max-link-speed = <1>;
262 status = "okay";
263};
264
265&pgc_gpu {
266 power-supply = <&sw1a_reg>;
267};
268
269&pgc_vpu {
270 power-supply = <&sw1c_reg>;
271};
272
273&qspi0 {
274 pinctrl-names = "default";
275 pinctrl-0 = <&pinctrl_qspi>;
276 status = "okay";
277
278 flash@0 {
279 compatible = "jedec,spi-nor";
280 #address-cells = <1>;
281 #size-cells = <1>;
282 reg = <0>;
283 spi-tx-bus-width = <1>;
284 spi-rx-bus-width = <4>;
285 m25p,fast-read;
286 spi-max-frequency = <50000000>;
287 };
288};
289
290&snvs_pwrkey {
291 status = "okay";
292};
293
294&uart1 {
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_uart1>;
297 assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
298 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
299 status = "okay";
300};
301
302&uart2 {
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_uart2>;
305 assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
306 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
307 status = "okay";
308};
309
310&uart3 {
311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_uart3>;
313 fsl,uart-has-rtscts;
314 assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
315 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
316 status = "okay";
317};
318
319&usb3_phy0 {
320 status = "okay";
321};
322
323&usb3_phy1 {
324 status = "okay";
325};
326
327&usb_dwc3_0 {
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_usb0>;
330 dr_mode = "otg";
331 hnp-disable;
332 srp-disable;
333 adp-disable;
334 maximum-speed = "high-speed";
335 status = "okay";
336};
337
338&usb_dwc3_1 {
339 dr_mode = "host";
340 status = "okay";
341};
342
343&usdhc1 {
344 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
345 assigned-clock-rates = <400000000>;
346 pinctrl-names = "default", "state_100mhz", "state_200mhz";
347 pinctrl-0 = <&pinctrl_usdhc1>;
348 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
349 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
350 vqmmc-supply = <&sw4_reg>;
351 bus-width = <8>;
352 non-removable;
353 no-sd;
354 no-sdio;
355 status = "okay";
356};
357
358&usdhc2 {
359 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
360 assigned-clock-rates = <200000000>;
361 pinctrl-names = "default", "state_100mhz", "state_200mhz";
362 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
363 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
364 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
365 bus-width = <4>;
366 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
367 wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
368 vmmc-supply = <&reg_usdhc2_vmmc>;
369 status = "okay";
370};
371
372&wdog1 {
373 pinctrl-names = "default";
374 pinctrl-0 = <&pinctrl_wdog>;
375 fsl,ext-reset-output;
376 status = "okay";
377};
378
379&iomuxc {
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_hog>;
382
383 pinctrl_hog: hoggrp {
384 fsl,pins = <
385 MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* TPM Reset */
386 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* USB2 Hub Reset */
387 >;
388 };
389
390 pinctrl_gpio: gpiogrp {
391 fsl,pins = <
392 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* GPIO0 */
393 MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /* GPIO1 */
394 MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* GPIO2 */
395 MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* GPIO3 */
396 MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* GPIO4 */
397 MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* GPIO5 */
398 MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* GPIO6 */
399 MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x19 /* GPIO7 */
400 >;
401 };
402
403 pinctrl_pcie0: pcie0grp {
404 fsl,pins = <
405 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x16 /* PCIE_PERST */
406 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 /* W_DISABLE */
407 >;
408 };
409
410 pinctrl_reg_usdhc2: regusdhc2gpiogrp {
411 fsl,pins = <
412 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
413 >;
414 };
415
416 pinctrl_fec1: fec1grp {
417 fsl,pins = <
418 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
419 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
420 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
421 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
422 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
423 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
424 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
425 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
426 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
427 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
428 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
429 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
430 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
431 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
432 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
433 MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
434 >;
435 };
436
437 pinctrl_i2c1: i2c1grp {
438 fsl,pins = <
439 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
440 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
441 >;
442 };
443
444 pinctrl_i2c2: i2c2grp {
445 fsl,pins = <
446 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
447 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
448 >;
449 };
450
451 pinctrl_i2c3: i2c3grp {
452 fsl,pins = <
453 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
454 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
455 >;
456 };
457
458 pinctrl_qspi: qspigrp {
459 fsl,pins = <
460 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
461 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
462 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
463 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
464 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
465 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
466 >;
467 };
468
469 pinctrl_ecspi2: ecspi2grp {
470 fsl,pins = <
471 MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19
472 MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19
473 MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19
474 >;
475 };
476
477 pinctrl_ecspi2_cs: ecspi2csgrp {
478 fsl,pins = <
479 MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
480 >;
481 };
482
483 pinctrl_uart1: uart1grp {
484 fsl,pins = <
485 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
486 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
487 >;
488 };
489
490 pinctrl_uart2: uart2grp {
491 fsl,pins = <
492 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
493 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
494 >;
495 };
496
497 pinctrl_uart3: uart3grp {
498 fsl,pins = <
499 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
500 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
501 MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
502 MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49
503 >;
504 };
505
506 pinctrl_usdhc1: usdhc1grp {
507 fsl,pins = <
508 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
509 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
510 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
511 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
512 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
513 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
514 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
515 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
516 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
517 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
518 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
519 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
520 >;
521 };
522
523 pinctrl_usdhc1_100mhz: usdhc1-100grp {
524 fsl,pins = <
525 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
526 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
527 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
528 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
529 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
530 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
531 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
532 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
533 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
534 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
535 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
536 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
537 >;
538 };
539
540 pinctrl_usdhc1_200mhz: usdhc1-200grp {
541 fsl,pins = <
542 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
543 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
544 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
545 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
546 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
547 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
548 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
549 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
550 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
551 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
552 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
553 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
554 >;
555 };
556
557 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
558 fsl,pins = <
559 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
560 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x19
561 >;
562 };
563
564 pinctrl_usdhc2: usdhc2grp {
565 fsl,pins = <
566 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
567 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
568 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
569 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
570 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
571 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
572 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
573 >;
574 };
575
576 pinctrl_usdhc2_100mhz: usdhc2-100grp {
577 fsl,pins = <
578 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
579 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
580 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
581 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
582 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
583 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
584 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
585 >;
586 };
587
588 pinctrl_usdhc2_200mhz: usdhc2-200grp {
589 fsl,pins = <
590 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
591 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
592 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
593 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
594 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
595 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
596 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
597 >;
598 };
599
600 pinctrl_usb0: usb0grp {
601 fsl,pins = <
602 MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x19
603 MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19
604 >;
605 };
606
607 pinctrl_wdog: wdoggrp {
608 fsl,pins = <
609 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
610 >;
611 };
612};